# US 11,309,012 B2 · Apparatuses and methods for staggered timing of targeted refresh operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,012 B2 - Document ID: US11309012B2 - Status: Granted - Kind: B2 - Application number: 17/187,002 - Filed: 2021-02-26 - Published: 2021-06-17 - Granted: 2022-04-19 - Earliest claimed: 2019-04-04 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Nathaniel J. Meier; James S. Rehmeyer - Web page: https://patentgrep.com/patent/US11309012B2 ## CPC - G11C 11/40618: {Refresh operations over multiple banks or interleaving} - G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh} - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G11C 11/40622: {Partial refresh of memory arrays} - G11C 11/408: Address circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. A memory device may include a number of memory banks, at least some of which may be simultaneously entered into a refresh mode. A given memory bank may perform an auto-refresh operation or a targeted refresh operation, which may draw less power than the auto-refresh operation. The timing of the targeted refresh operations may be staggered between the refreshing memory banks, such that a portion of the refreshing memory banks are performing a targeted refresh operation simultaneously with a portion of the refreshing memory banks performing an auto-refresh operation. ## Claims ### Claim 1 An apparatus comprising: a plurality of memory banks, each comprising a plurality of word lines; and a plurality of refresh control circuits, each associated with a respective one of the plurality of memory banks, wherein the plurality of refresh control circuits receive a refresh signal in common and each provide a refresh address responsive to the refresh signal, wherein the refresh address is associated with a number of the plurality of word lines, and wherein at least one of the refresh addresses is associated with fewer word lines than a remainder of the refresh addresses. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising a plurality of row decoders, each configured to refresh an associated one of the plurality of memory banks based on the refresh address. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the plurality of refresh control circuits are each configured to determine an aggressor address, and wherein the at least one of the refresh addresses associated with the fewer word lines is based on the aggressor address. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the plurality of refresh control circuits are each configured to provide a plurality of refresh addresses responsive to the refresh signal, each associated with an activation of a pump signal. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the proportion of refresh addresses associated with the fewer word lines is different during some activations of the pump signal. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the plurality of refresh circuits are configured to provide the plurality of refresh addresses approximately simultaneously. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the refresh address associated with the fewer word lines is a targeted refresh address and wherein the remainder of the plurality of refresh addresses are auto-refresh addresses. ### Claim 8 An apparatus comprising: a first memory bank including a first plurality of word lines; a second memory bank including a second plurality of word lines; a first refresh control circuit associated with the first memory bank, wherein responsive to a refresh signal, the first refresh control circuit is configured to provide a first type of refresh address associated with a first number of wordlines as part of a first type of refresh operation; a second refresh control circuit associated with the second memory bank wherein responsive to the refresh signal, the second refresh control circuit is configured to provide a second type of refresh address associated with a second number of word lines as part of a second type of refresh operation, wherein the first type of refresh operation draws less power than the second type of refresh operation. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the first type of refresh operation is a targeted refresh operation and the second type of refresh operation is an auto-refresh operation. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the first number of word lines is less than the second number of word lines. ### Claim 11 (depends on 8) The apparatus of claim 8, wherein responsive to the refresh signal the first refresh control circuit is configured to provide the first type of refresh address followed by the second type of refresh address and wherein responsive to the refresh signal the second refresh control circuit is configured to provide the second type of refresh address followed by the first type of refresh address. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein each refresh address is associated with an activation of a pump signal. ### Claim 13 (depends on 8) The apparatus of claim 8, wherein the first refresh control circuit is configured to determine an aggressor address and wherein the first type of refresh address is based on the determined aggressor address. ### Claim 14 (depends on 8) The apparatus of claim 8, further comprising: a first row decoder configured to refresh the first number of word lines in the first memory bank responsive to the first type of refresh address; and a second row decoder configured to refresh the second number of word lines in the second memory bank responsive to the second type of refresh address. ### Claim 15 A method comprising: receiving a refresh signal at a plurality of refresh control circuits; generating a plurality of refresh addresses with the plurality of refresh control circuits responsive to the refresh signal, wherein the plurality of refresh addresses includes a first type of refresh address associated with a first number of word lines and a second type of refresh address associated with a second number of wordlines; refreshing a plurality of banks, based on one or more of the plurality of refresh addresses, wherein refreshing one of the plurality of banks associated with the first type of refresh address draws less power than refreshing one of the plurality of banks associated with the second type of address. ### Claim 16 (depends on 15) The method of claim 15, further comprising determining an aggressor address and generating the first type of refresh address based on the aggressor address. ### Claim 17 (depends on 15) The method of claim 15, wherein responsive to each refresh signal each of the plurality of refresh control circuits provide a plurality of refresh addresses including the first type of refresh address and the second type of refresh address. ### Claim 18 (depends on 17) The method of claim 17, further comprising generating a plurality of activations of a pump signal, and wherein each of the plurality of refresh addresses from one of the plurality of refresh control circuits is associated with one of the plurality of activations of the pump signal. ### Claim 19 (depends on 15) The method of claim 15 further comprising: refreshing the first type of refresh address as part of a targeted refresh operation; and refreshing the second type of refresh address as part of an auto-refresh operation. ### Claim 20 (depends on 15) The method of claim 15, further comprising refreshing at least one of the plurality of banks based on the first type of refresh address and approximately simultaneously refreshing a remainder of the plurality of banks based on the second type of refresh address.