# US 11,309,004 B2 · Mechanism to improve driver capability with fine tuned calibration resistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,004 B2 - Document ID: US11309004B2 - Status: Granted - Kind: B2 - Application number: 17/306,893 - Filed: 2021-05-03 - Published: 2021-10-28 - Granted: 2022-04-19 - Earliest claimed: 2020-04-24 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Ankur Agrawal; Simarpreet Kaur - Web page: https://patentgrep.com/patent/US11309004B2 ## CPC - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]} - G11C 29/022: {in I/O circuitry} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/06: Acceleration testing - G11C 29/12005: {comprising voltage or current generators} - G11C 29/4401: {for self repair} - G11C 2029/1206: {Location of test circuitry on chip or wafer} - G11C 2029/5002: {Characteristic} - G11C 2029/5004: {Voltage} - G11C 2207/2254: Calibration - G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Aspects of a storage device including a controller, a calibration resistor and a die having an output driver and a calibration circuit are provided, which allow for an output impedance of the output driver to be calibrated to a lower impedance than a minimum required for reading data across PVT variations of the die at maximum loading of the controller. To check whether slow corners may operate using the lower impedance, the controller determines whether the output impedance of the output driver can be calibrated to the lower impedance at a maximum temperature and minimum voltage applied to the die, or whether a calibration code generated from the calibration circuit exceeds a threshold at a nominal temperature and voltage applied to the die. Thus, slow corners are screened out from lower impedance use, while faster devices are designed with a smaller calibration resistance to benefit from increased memory and speed. ## Claims ### Claim 1 A storage device, comprising: a calibration resistor having a resistance that enables a calibration circuit to calibrate an output impedance of an output driver to a lower impedance than a minimum impedance, the minimum impedance being required by a controller to read stored data across process, voltage and temperature variations of a die at maximum loading of the controller. ### Claim 2 (depends on 1) The storage device of claim 1, further comprising the controller configured to command the calibration circuit to calibrate the output impedance. ### Claim 3 (depends on 1) The storage device of claim 1, wherein the output driver further comprises a plurality of parallel pull-up driver transistors and a plurality of parallel pull-down driver transistors, and wherein the calibration circuit is further configured to set an impedance of the parallel pull-up driver transistors and an impedance of the parallel pull-down driver transistors to the resistance of the calibration resistor. ### Claim 4 (depends on 3) The storage device of claim 3, wherein the output driver further comprises a plurality of parallel second pull-up driver transistors coupled in parallel with the pull-up driver transistors and a plurality of parallel second pull-down driver transistors coupled in parallel with the pull-down driver transistors, and wherein the calibration circuit is further configured to set an impedance of the parallel second pull-up driver transistor and an impedance of the parallel second pull-down driver transistor to the resistance of the calibration resistor. ### Claim 5 (depends on 1) The storage device of claim 1, wherein the output driver further comprises a plurality of parallel pull-up driver transistors and a plurality of parallel pull-down driver transistors, and wherein the calibration circuit is further configured to control the output impedance of the output driver by controlling the pull-up driver transistors and the pull-down driver transistors. ### Claim 6 (depends on 5) The storage device of claim 5, wherein the calibration circuit comprises a plurality of parallel pull-up calibration transistors, the calibration circuit being further configured to control the pull-up calibration transistors based on the calibration resistor and control the pull-up driver transistors based on the control of the pull-up calibration transistors. ### Claim 7 (depends on 6) The storage device of claim 6, wherein the calibration circuit comprises an output pulled up by the pull-up calibration transistors and loaded by the calibration resistor, the calibration circuit further comprising a feedback circuit configured to control the pull-up calibration transistors based on the output of the calibration circuit. ### Claim 8 (depends on 7) The storage device of claim 7, wherein the feedback circuit is configured to set an impedance of the parallel pull-up calibration transistors to the resistance of the calibration resistor. ### Claim 9 A storage device, comprising: a controller configured to determine whether an output impedance of an output driver can be calibrated to an impedance lower than a threshold when a die has a maximum temperature and a minimum voltage. ### Claim 10 (depends on 9) The storage device of claim 9, further comprising a calibration resistor, wherein the calibration resistor has a resistance that would enable a calibration circuit to calibrate the output impedance to a lower impedance than a minimum impedance, the minimum impedance being required by the controller to read stored data across process, voltage and temperature variations of the die at maximum loading of the controller. ### Claim 11 (depends on 9) The storage device of claim 9, wherein the controller is configured to command a calibration circuit to calibrate the output impedance. ### Claim 12 (depends on 9) The storage device of claim 9, wherein the threshold is a function of a resistance of a calibration resistor. ### Claim 13 (depends on 9) The storage device of claim 9, further comprising a calibration circuit, wherein the output driver further comprises a plurality of parallel pull-up driver transistors and a plurality of parallel pull-down driver transistors, and wherein the calibration circuit is further configured to set an impedance of the parallel pull-up driver transistors and an impedance of the parallel pull-down driver transistors to a resistance of a calibration resistor. ### Claim 14 A storage device, comprising: a controller configured to determine whether a calibration code exceeds a threshold when a die has a nominal temperature and a nominal voltage. ### Claim 15 (depends on 14) The storage device of claim 14, further comprising a calibration resistor, wherein the calibration resistor has a resistance that would enable a calibration circuit to calibrate an output impedance of an output driver to a lower impedance than a minimum impedance, the minimum impedance being required by the controller to read stored data across process, voltage and temperature variations of the die at maximum loading of the controller. ### Claim 16 (depends on 14) The storage device of claim 14, wherein the controller is configured to command a calibration circuit to calibrate an output impedance of an output driver. ### Claim 17 (depends on 14) The storage device of claim 14, further comprising an output driver and a calibration circuit, wherein the output driver further comprises a plurality of parallel pull-up driver transistors and a plurality of parallel pull-down driver transistors, and wherein the calibration circuit is further configured to set an impedance of the parallel pull-up driver transistors and an impedance of the parallel pull-down driver transistors to a resistance of a calibration resistor. ### Claim 18 (depends on 14) The storage device of claim 14, further comprising a calibration circuit, wherein the calibration circuit comprises an output loaded by a calibration resistor, a plurality of pull-up calibration transistors pulling up the output, and a feedback circuit configured to generate the calibration code based on the output of the calibration circuit. ### Claim 19 (depends on 18) The storage device of claim 18, wherein the feedback circuit is further configured to control the pull-up calibration transistors with the calibration code. ### Claim 20 (depends on 14) The storage device of claim 14, further comprising an output driver and a calibration circuit, wherein the output driver further comprises a plurality of parallel pull-up driver transistors and a plurality of parallel pull-down driver transistors, and wherein the calibration circuit is further configured to control the parallel pull-up driver transistors and the parallel pull-down driver transistors with the calibration code.