# US 11,309,001 B2 · Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

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- Number: US 11,309,001 B2
- Document ID: US11309001B2
- Status: Granted
- Kind: B2
- Application number: 17/071,107
- Filed: 2020-10-15
- Published: 2021-01-28
- Granted: 2022-04-19
- Earliest claimed: 2018-05-29
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Kang-Yong Kim
- Web page: https://patentgrep.com/patent/US11309001B2

## CPC

- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/109: {Control signal input circuits}
- G11C 7/225: {Clock input buffers}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- H03K 5/1565: {the output pulses having a constant duty cycle}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

## Claims

### Claim 1

A method, comprising:
issuing from a controller via a command/address bus, commands to a memory to perform a first duty cycle monitor sequence to determine a first duty cycle result;
changing with the controller, a duty cycle adjuster code stored in the memory to decrease the duty cycle adjuster code to decrease a high duty cycle based on the first duty cycle result by providing a mode register write command to the memory via the command/address bus;
issuing from the controller via the command/address bus commands to the memory to perform a second duty cycle monitor sequence to determine a second duty cycle result; and
changing the duty cycle adjuster code stored in the memory to increase the duty cycle adjuster code to increase the high duty cycle based on the second duty cycle result by providing a second mode register write command to the memory via the command/address bus, wherein a magnitude of the increase is different than a magnitude of the decrease.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first duty cycle result comprises: a first result from a first duty cycle input flip condition; and
a second result from a second duty cycle input flip condition that is different than the first duty cycle input flip condition.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first duty cycle result indicates a first high duty cycle greater than 50% and the second duty cycle result indicates a second high duty cycle less than 50%.

### Claim 4 (depends on 1)

The method of claim 1, further comprising issuing commands to the memory to perform a third duty cycle monitor sequence to determine a third duty cycle result.

### Claim 5 (depends on 4)

The method of claim 4, wherein issuing commands to the memory to perform the third duty cycle monitor sequence is performed before changing the duty cycle adjuster code.

### Claim 6 (depends on 1)

The method of claim 1, wherein changing the duty cycle adjuster code comprises changing one or more bits stored in a mode register.

### Claim 7 (depends on 1)

The method of claim 1; wherein the magnitude of the increase is greater than the magnitude of the decrease.

### Claim 8 (depends on 1)

The method of claim 1, further comprising providing a clock signal from the controller to the memory via a clock bus.

### Claim 9 (depends on 8)

The method of claim 8, wherein the duty cycle adjuster code is based, at least in part, on the clock signal.

### Claim 10

A method, comprising:
changing a duty cycle adjuster code stored in a memory by a fast speed to change a duty cycle based on a first duty cycle result of a first duty cycle monitor sequence; and
changing the duty cycle adjuster code stored in the memory by a slow speed to change the duty cycle based on a second duty cycle result of a second duty cycle monitor sequence,
wherein changing the duty cycle adjuster code comprises providing the duty cycle adjuster code and a mode register write command to the memory by a controller via a command/address bus.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first duty cycle result indicates a high duty cycle less than 50% and the second duty cycle result indicates a high duty cycle greater than 50%.

### Claim 12 (depends on 10)

The method of claim 10, wherein the fast speed corresponds to a first number of steps of a duty cycle adjuster range and the slow speed corresponds to a second number of steps of the duty cycle adjuster range, wherein the second number is less than the first number.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first number is double the second number.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
issuing commands to the memory to perform the first duty cycle monitor sequence to determine the first duty cycle result; and
issuing commands to the memory to perform the second duty cycle monitor sequence to determine the second duty cycle result.

### Claim 15 (depends on 10)

The method of claim 10, further comprising issuing commands to the memory to read at least one of the first duty cycle result or the second duty cycle result.

### Claim 16 (depends on 15)

The method of claim 15, wherein at least one of the first duty cycle result or the second duty cycle result are stored as one or more bits in a mode register.

### Claim 17 (depends on 10)

The method of claim 10, further comprising providing a clock signal from the controller to the memory via a clock bus.

### Claim 18

An apparatus, comprising:
a memory;
a memory controller coupled to the memory, the memory controller configured to:
issue commands to the memory to perform a first duty cycle monitor sequence to determine a first duty cycle result;
change a duty cycle adjuster code of the memory by a first step size to change a duty cycle based on the first duty cycle result;
issue commands to the memory to perform a second duty cycle monitor sequence to determine a second duty cycle result; and
change the duty cycle adjuster code of the memory by a second step size to change a duty cycle based on the second duty cycle result, wherein the second step size is different than the first step size;
a command/address bus;
a data bus; and
a clock bus, wherein the memory controller is coupled to the memory through the command/address bus, the data bus, and the clock bus.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the memory comprises a mode register, wherein the duty cycle adjuster code is stored as one or more bits in the mode register.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the second step size is less than the first step size.

### Claim 21 (depends on 18)

The apparatus of claim 18, wherein the first duty cycle result indicates a first high duty cycle greater than 50% and the second duty cycle result indicates a second high duty cycle less than 50%.

### Claim 22 (depends on 18)

The apparatus of claim 18, wherein changing the duty cycle adjuster code of the memory by the first step size decreases a high duty cycle and changing the duty cycle adjuster code of the memory by the second step size increases the duty cycle adjuster code to increase the high duty cycle.