# US 11,308,997 B1 · Method and system for direct access to flash modules

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- Number: US 11,308,997 B1
- Document ID: US11308997B1
- Status: Granted
- Kind: B1
- Application number: 17/228,205
- Filed: 2021-04-12
- Granted: 2022-04-19
- Earliest claimed: 2021-02-03
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Xiaodong Xu; Yi Chen
- Web page: https://patentgrep.com/patent/US11308997B1

## CPC

- G11C 7/1045: {Read-write mode select circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/109: {Control signal input circuits}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- G11C 29/1201: {comprising I/O circuitry}
- G11C 29/14: Implementation of control logic, e.g. test mode decoders
- G11C 29/36: Data generation devices, e.g. data inverters
- G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
- G11C 29/56008: {Error analysis, representation of errors}
- G11C 2029/3602: {Pattern generator}
- G11C 2029/5602: {Interface to device under test}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes a substrate, a controller disposed on the substrate and providing an external interface, and a plurality of flash memory dies connected to the controller through an internal interface. The external interface includes at least a bypass pin, a mode selection pin, and a data pin, and is used by an external host to direct access the plurality of flash memory dies through the controller. The bypass pin is used to enable the controller to enter in a direct access state in which the mode selection pin and the data pin are operational; and the mode selection pin is used to trigger the controller to receive a mode code on the data pin and to receive a mode code value on the data pin. The mode code indicates one of a plurality of predetermined input-output modes of the controller in the direct access state, and the mode code value determining information under the predetermined input-output mode indicated by the mode code.

## Claims

### Claim 1

A memory device, comprising:
a substrate;
a controller disposed on the substrate and providing an external interface; and
a plurality of flash memory dies connected to the controller through an internal interface,
wherein:
the external interface includes at least a bypass pin, a mode selection pin, and a data pin and is used by an external host to direct access the plurality of flash memory dies through the controller;
the bypass pin is used to enable the controller to enter in a direct access state in which the mode selection pin and the data pin are operational; and
the mode selection pin is used to trigger the controller to receive a mode code on the data pin, the mode code indicating one of a plurality of predetermined input-output modes of the controller in the direct access state, and to receive a mode code value on the data pin, the mode code value determining information under the predetermined input-output mode indicated by the mode code.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein the external interface further includes a clock pin and a ready pin for bus operations while the controller is in the direct access state.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein:
the substrate includes a plurality of test pads respectively connected to the bypass pin, the mode selection pin, the data pin, the clock pin, and the ready pin; and
the external host uses the plurality of test pads to connect to the bypass pin, the mode selection pin, the data pin, the clock pin, and the ready pin.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein:
the external interface further includes seven additional data pins, and the seven additional data pins in combination with the data pin are used for a byte-wider data transmission on the external interface via a corresponding byte-wider parallel data bus.

### Claim 5 (depends on 1)

The memory device according to claim 1, wherein:
the predetermined input-output modes include a die-selection mode; and
the mode code of the die-selection mode indicates that one or more of the plurality of flash memory dies are selected for direct access, and the mode code value following the mode code of the die-selection mode determine the one or more of the plurality of flash memory dies.

### Claim 6 (depends on 5)

The memory device according to claim 5, wherein:
the predetermined input-output modes further include a data-rate switch mode; and
the mode code of the data-rate switch mode indicates whether a data rate switch is to be performed, and the mode code value following the mode code of the data-rate switch mode determines a single data rate (SDR) or a double data rate (DDR) to be switched to.

### Claim 7 (depends on 5)

The memory device according to claim 5, wherein:
the predetermined input-output modes further include a pattern-selection mode; and
the mode code of the pattern-selection mode indicates whether a data pattern is to be generated by the controller to improve throughput, and the mode code value following the mode code of the pattern-selection mode determine the data pattern to be generated by the controller.

### Claim 8 (depends on 5)

The memory device according to claim 5, wherein:
the predetermined input-output modes further include a command-in mode, an address-in mode, a data-in mode, and a data-out mode;
the mode code of the command-in mode indicates a command-in cycle following the mode code of the command-in mode on the data pin;
the mode code of the address-in mode indicates an address-in cycle following the mode code of the address-in mode on the data pin;
the mode code of the data-in mode indicates a data-in cycle following the mode code of the data-in mode on the data pin; and
the mode code of the data-out mode indicates a data-out cycle following the mode code of the data-out mode on the data pin.

### Claim 9 (depends on 1)

The memory device according to claim 1, wherein the mode code is a 3-bit code or a 4-bit code.

### Claim 10 (depends on 1)

The memory device according to claim 1, wherein the plurality of flash memory dies are NAND memory dies, the plurality of flash memory dies and the controller are packaged in one eMMC or UFS package.

### Claim 11 (depends on 1)

The memory device according to claim 1, wherein:
each of the flash memory dies includes a test register to be set by the controller to cause the flash memory die to use a reduce low pin count (RLPC) standard to communicate over the internal interface, such that data on the data pin is relayed to and/or from the flash memory die based on the RLPC standard.

### Claim 12 (depends on 11)

The memory device according to claim 11, wherein the controller includes:
an input/output logic to receive the data on the data pin;
an RLPC translation logic to convert the data on the data pin to signals on the internal interface based on the RLPC standard; and
a control logic to set the predetermined input-output mode based on the mode code.

### Claim 13

A method for testing a memory device having a substrate, a controller disposed on the substrate and providing an external interface, and a plurality of flash memory dies connected to the controller through an internal interface, the method comprising:
operating a bypass pin in the external interface to enable the controller to enter in a direct access state in which a mode selection pin and a data pin in the external interface are operational;
providing a plurality of predetermined input-output modes of the controller in the direct access state;
triggering, by the mode selection pin in the external interface, the controller to receive a mode code, which indicates one of the plurality of predetermined input-output modes, on the data pin in the external interface, and to receive a mode code value, which determines information under the predetermined input-output mode indicated by the mode code, on the data pin; and
directly accessing, by use of the data pin, the plurality of flash memory dies through the controller.

### Claim 14 (depends on 13)

The method according to claim 13, wherein:
the external interface further includes a clock pin and a ready pin, and the method further includes performing bus operations, by use of the clock pin and the ready pin, while the controller is in the direct access state;
the substrate includes a plurality of test pads respectively connected to the bypass pin, the mode selection pin, the data pin, the clock pin, and the ready pin, and the method further includes using the plurality of test pads to connect to the bypass pin, the mode selection pin, the data pin, the clock pin, and the ready pin.

### Claim 15 (depends on 13)

The method according to claim 13, wherein the predetermined input-output modes include a die-selection mode, and the method further includes:
placing the mode code of the die-selection mode on the data pin after triggering the controller to receive a mode code, to indicate that one or more of the plurality of flash memory dies are selected for direct access, and sending the mode code value following the mode code of the die-selection mode to select the one or more of the plurality of flash memory dies.

### Claim 16 (depends on 13)

The method according to claim 13, wherein the predetermined input-output modes further include a data-rate switch mode, and the method further includes:
placing the mode code of the data-rate switch mode on the data pin after triggering the controller to receive a mode code, to indicate whether a data rate switch is to be performed, and sending the mode code value following the mode code of the data-rate switch mode to determine a single data rate (SDR) or a double data rate (DDR) to be switched to.

### Claim 17 (depends on 13)

The method according to claim 13, wherein the predetermined input-output modes further include a pattern-selection mode, and the method further includes:
placing the mode code of the pattern-selection mode on the data pin after triggering the controller to receive a mode code, to indicate whether a data pattern is to be generated by the controller to improve throughput, and sending the mode code value following the mode code of the pattern-selection mode to determine the data pattern to be generated by the controller.

### Claim 18 (depends on 15)

The method according to claim 15, wherein the predetermined input-output modes further include a command-in mode, an address-in mode, a data-in mode, and a data-out mode; and the method further includes:
placing the mode code of the command-in mode indicating a command-in cycle following the mode code of the command-in mode on the data pin;
placing the mode code of the address-in mode indicating an address-in cycle following the mode code of the address-in mode on the data pin;
placing the mode code of the data-in mode indicating a data-in cycle following the mode code of the data-in mode on the data pin; and
placing the mode code of the data-out mode indicating a data-out cycle following the mode code of the data-out mode on the data pin.

### Claim 19

A controller for controlling a plurality of flash memory dies, comprising:
an external interface; and
an internal interface, through which the plurality of flash memory dies are connected to the controller;
wherein:
the external interface includes at least a bypass pin, a mode selection pin, and a data pin and is used by an external host to direct access the plurality of flash memory dies through the controller;
the bypass pin is used to enable the controller to enter in a direct access state in which the mode selection pin and the data pin are operational; and
the mode selection pin is used to trigger the controller to receive a mode code on the data pin, the mode code indicating one of a plurality of predetermined input-output modes of the controller in the direct access state, and to receive a mode code value on the data pin, the mode code value determining information under the predetermined input-output mode indicated by the mode code.

### Claim 20 (depends on 19)

The controller according to claim 19, wherein:
the external interface further includes seven additional data pins, and the seven additional data pins in combination with the data pin are used for a byte-wider data transmission on the external interface via a corresponding byte-wider parallel data bus;
the controller further includes:
an input/output logic to receive the data on the data pin;
a reduce low pin count (RLPC) translation logic to convert the data on the data pin to signals on the internal interface based on the RLPC standard; and
a control logic to set the predetermined input-output mode based on the mode code.