# US 11,308,995 B2 · Semiconductor apparatus and semiconductor memory apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,308,995 B2 - Document ID: US11308995B2 - Status: Granted - Kind: B2 - Application number: 17/148,201 - Filed: 2021-01-13 - Published: 2022-01-27 - Granted: 2022-04-19 - Earliest claimed: 2020-07-21 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Hyun Chul Lee - Web page: https://patentgrep.com/patent/US11308995B2 ## CPC - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)} - G11C 16/225: {Preventing erasure, programming or reading when power supply voltages are outside the required ranges} - G11C 16/30: Power supply circuits - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor apparatus including a sudden power detection circuit, a power-on reset circuit, and a driving circuit. The sudden power detection circuit configured to detect an external power supply voltage and generate a sudden power detection signal. The power-on reset circuit configured to detect the voltage level of the external power supply voltage according to a reset reference voltage and generate a power-on reset signal. The driving circuit configured to perform a sudden power-off operation and a power-on reset operation. ## Claims ### Claim 1 A semiconductor apparatus comprising: a sudden power detection circuit enabled based on an enable signal and configured to detect a voltage level of an external power supply voltage and generate a sudden power detection signal; a power-on reset circuit configured to set a reset reference voltage for a power-on reset operation based on the enable signal and a power-on reset signal, to detect the voltage level of the external power supply voltage according to the reset reference voltage, and to generate the power-on reset signal; and a driving circuit configured to perform a sudden power-off operation based on the sudden power detection signal and to perform the power-on reset operation based on the power-on reset signal. ### Claim 2 (depends on 1) The semiconductor apparatus according to claim 1, wherein the sudden power-off operation includes a discharging operation for a specific node of the driving circuit, and the power-on reset operation includes an initialization operation for the driving circuit. ### Claim 3 (depends on 1) The semiconductor apparatus according to claim 1, wherein the reset reference voltage includes a first reset reference voltage corresponding to a power-up period of the external power supply voltage and a second reset reference voltage corresponding to a power-down period of the external power supply voltage. ### Claim 4 (depends on 3) The semiconductor apparatus according to claim 3, wherein the first reset reference voltage and the second reset reference voltage have different voltage levels. ### Claim 5 (depends on 3) The semiconductor apparatus according to claim 3, wherein a voltage level of the first reset reference voltage is higher than a voltage level of the second reset reference voltage. ### Claim 6 (depends on 3) The semiconductor apparatus according to claim 3, wherein the sudden power detection circuit comprises: a voltage division circuit configured to generate a divided voltage by dividing a voltage level of the external power supply voltage based on the enable signal; and a voltage comparison circuit configured to compare the divided voltage and a sudden power reference voltage and generate the sudden power detection signal. ### Claim 7 (depends on 6) The semiconductor apparatus according to claim 6, wherein a voltage level of the sudden power reference voltage includes a voltage level between a voltage level of the first reset reference voltage and a voltage level of the second reset reference voltage. ### Claim 8 (depends on 1) The semiconductor apparatus according to claim 1, wherein the power-on reset circuit comprises: a voltage detection circuit configured to set the reset reference voltage based on the enable signal and the power-on reset signal and detect the external power supply voltage based on the set reset reference voltage; and a signal output circuit configured to output the power-on reset signal based on an output signal of the voltage detection circuit. ### Claim 9 (depends on 8) The semiconductor apparatus according to claim 8, wherein the voltage detection circuit comprises: a resistance adjustment circuit configured to adjust a resistance value for a voltage drop of the external power supply voltage based on the enable signal and the power-on reset signal; and a voltage sensing circuit configured to sense the external power supply voltage, which has been dropped by the resistance value adjusted by the resistance adjustment circuit, based on the reset reference voltage. ### Claim 10 (depends on 8) The semiconductor apparatus according to claim 8, wherein the signal output circuit comprises: a loading circuit configured to receive the external power supply voltage; and an output circuit configured to output the power-on reset signal based on an output signal of the loading circuit and the output signal of the voltage detection circuit. ### Claim 11 (depends on 1) The semiconductor apparatus according to claim 1, wherein the power-on reset circuit further comprises: a skew adjustment circuit configured to further receive skew control signals corresponding to a process, voltage, temperature (PVT) skew, and to adjust the reset reference voltage based on the skew control signals. ### Claim 12 (depends on 11) The semiconductor apparatus according to claim 11, wherein the skew adjustment circuit selectively controls a resistance path of the external power supply voltage based on the skew control signals. ### Claim 13 A semiconductor memory apparatus comprising: a sudden power detection circuit enabled based on an enable signal and configured to detect a voltage level of an external power supply voltage and generate a sudden power detection signal; a power-on reset circuit configured to set a reset reference voltage for a power-on reset operation based on the enable signal and a power-on reset signal, to detect the voltage level of the external power supply voltage according to the reset reference voltage, and to generate the power-on reset signal; and a discharging circuit configured to perform a discharging operation on a line connected to a memory cell, based on the sudden power detection signal. ### Claim 14 (depends on 13) The semiconductor memory apparatus according to claim 13, further comprising: a memory cell array circuit including a plurality of memory cells that are connected to a word line, a bit line, and a source line and are configured to store data, wherein the discharging circuit performs the discharging operation on at least one of the word line, the bit line, and the source line based on the sudden power detection signal. ### Claim 15 (depends on 14) The semiconductor memory apparatus according to claim 14, further comprising: a voltage supply circuit configured to supply internal power supply voltages to the word line, the bit line, and the source line; and a page buffer circuit configured to transmit and receive (transmit/receive) data to and from (to/from) the memory cell array circuit through the bit line, wherein at least one of the voltage supply circuit and the page buffer circuit is initialized based on the power-on reset signal. ### Claim 16 (depends on 13) The semiconductor memory apparatus according to claim 13, wherein the reset reference voltage includes a first reset reference voltage corresponding to a power-up period of the external power supply voltage and a second reset reference voltage corresponding to a power-down period of the external power supply voltage. ### Claim 17 (depends on 16) The semiconductor memory apparatus according to claim 16, wherein the first reset reference voltage and the second reset reference voltage have different voltage levels. ### Claim 18 (depends on 16) The semiconductor memory apparatus according to claim 16, wherein a voltage level of the first reset reference voltage is higher than a voltage level of the second reset reference voltage. ### Claim 19 (depends on 13) The semiconductor memory apparatus according to claim 13, wherein the power-on reset circuit comprises: a voltage detection circuit configured to set the reset reference voltage based on the enable signal and the power-on reset signal and detect the external power supply voltage based on the set reset reference voltage; and a signal output circuit configured to output the power-on reset signal based on an output signal of the voltage detection circuit. ### Claim 20 (depends on 19) The semiconductor memory apparatus according to claim 19, wherein the voltage detection circuit comprises: a resistance adjustment circuit configured to adjust a resistance value for a voltage drop of the external power supply voltage based on the enable signal and the power-on reset signal; and a voltage sensing circuit configured to sense the external power supply voltage, which has been dropped by the resistance value adjusted by the resistance adjustment circuit, based on the reset reference voltage.