# US 11,308,919 B2 · Multiple display synchronization

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- Number: US 11,308,919 B2
- Document ID: US11308919B2
- Status: Granted
- Kind: B2
- Application number: 16/972,397
- Filed: 2019-05-23
- Published: 2021-07-29
- Granted: 2022-04-19
- Earliest claimed: 2018-06-04
- Assignees: Microsoft Technology Licensing, LLC
- Applicants: Microsoft Technology Licensing, LLC
- Inventors: Matthew Morris; Ying Zheng; Rajesh Dighde
- Web page: https://patentgrep.com/patent/US11308919B2

## CPC

- G09G 5/12: Synchronisation between the display unit and other units, e.g. other display units, video-disc players
- G06F 3/1431: {using a single graphics controller}
- G06F 3/1438: {using more than one graphics controller}
- G06F 3/1446: {display composed of modules, e.g. video walls}
- G09G 2300/026: Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2340/0435: Change or adaptation of the frame rate of the video stream
- G09G 2360/04: Display device controller operating with a plurality of display units
- G09G 2370/04: Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
- G09G 2370/14: Use of low voltage differential signaling [LVDS] for display data communication
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A device (100) includes a plurality of display panels (102), a plurality of display controllers (116), each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, each respective display controller of the plurality of display controllers being configured to generate a timing indication (134), and a processor (136) coupled to the plurality of display controllers to receive the timing indications from the plurality of display controllers. Each timing indication is indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel. The processor is configured to delay a refresh of the plurality of display panels until the timing indication is received from each respective display controller of the plurality of display controllers to synchronize the plurality of display panels.

## Claims

### Claim 1

A device comprising:
a plurality of display panels;
a plurality of display controllers, each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, each respective display controller of the plurality of display controllers being configured to generate a timing indication, wherein a first display controller of the plurality of display controllers is a primary display controller and a second display controller of the plurality of display controllers is a secondary display controller and the secondary display controller is configured to provide a secondary timing indication to the primary display controller; and
a processor coupled to the plurality of display controllers to receive a primary timing indication from the primary display controller;
wherein the secondary timing indication is indicative of the secondary display controller residing in a state ready for refresh of a corresponding display panel and the primary timing indication is indicative of the first display controller residing in a state ready for refresh of a corresponding display and having received the secondary timing indication from the secondary display controller, wherein directing the plurality of display controllers comprises generating, with the processor, a trigger signal via an AND operation of the processor, and
wherein the processor is configured to delay a refresh of the plurality of display panels until the primary timing indication is received from the primary display controller to synchronize the plurality of display panels.

### Claim 2 (depends on 1)

The device of claim 1, wherein the processor is configured to send a refresh instruction to each display controller of the plurality of display controllers upon receipt of the primary timing indication from the primary display controller.

### Claim 3 (depends on 2)

The device of claim 2, wherein:
the processor is configured to generate image data to be rendered on the plurality of display panels; and
the processor is configured to send the refresh instruction via a command interface between the processor and the respective display controller.

### Claim 4 (depends on 1)

The device of claim 1, wherein the processor is configured to send a refresh trigger signal to each display controller of the plurality of display controllers upon receipt of the primary timing indication from the primary display controller.

### Claim 5 (depends on 4)

The device of claim 4, wherein:
the secondary timing indication is provided as a timing signal.

### Claim 6 (depends on 5)

The device of claim 5, further comprising an application processor configured to generate image data to be rendered on the plurality of display panels of the device, wherein the signal processor is configured to synchronize the plurality of display panels when the application processor is not generating the image data.

### Claim 7 (depends on 6)

The device of claim 6, wherein the application processor is further configured to provide an enable signal to each display controller of the plurality of display controllers to control whether the plurality of display controllers are responsive to an output from the signal processor indicative of the AND operation.

### Claim 8 (depends on 5)

The device of claim 5, wherein the processor comprises a signal processor.

### Claim 9 (depends on 5)

The device of claim 5, wherein the signal processor comprises a counter, the counter being configured to track a time elapsed since a last refresh.

### Claim 10 (depends on 1)

The device of claim 1, wherein:
each display controller of the plurality of display controllers is configured to receive image data via an image data interface; and
each timing indication is provided as a respective timing signal on a respective dedicated line separate from the image data interface.

### Claim 11

A method of synchronizing a plurality of display panels of a device, the method comprising:
detecting, with a primary display controller, one or more secondary timing indications, each timing indication of the one or more timing indications being generated by a respective secondary display controller of a plurality of display controllers, the primary display controller and each secondary display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, wherein each timing indication is indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel; and
directing, with the primary display controller, the primary display controller and the plurality of secondary display controllers to refresh the plurality of display panels once the secondary timing indication from each respective secondary display controller of the plurality of display controllers is detected by the primary display controller to synchronize the plurality of display panels wherein directing the plurality of display controllers comprises generating, with the processor, a trigger signal via an AND operation of the processor.

### Claim 12 (depends on 11)

The method of claim 11, further comprising generating, with a processor in communication with at least the primary display controller, image data to be rendered on the plurality of display panels, wherein directing the primary display controller and the secondary display controllers of the plurality of display controllers comprises sending a refresh instruction from the processor via a command interface between the processor and the respective display controller.

### Claim 13 (depends on 12)

The method of claim 12, further comprising sending an enable signal from an application processor of the device to enable the processor to direct the plurality of display controllers.

### Claim 14 (depends on 11)

The method of claim 11, further comprising detecting a primary timing indication with a processor, wherein detecting the primary timing indication comprises monitoring a respective dedicated line separate from an image data interface via which the plurality of display controllers are configured to receive image data.

### Claim 15

A device comprising:
a plurality of display controllers, each respective display controller of the plurality of display controllers being configured to generate a timing indication, wherein a first display controller of the plurality of display controllers is a primary display controller and a second display controller of the plurality of display controllers is a secondary display controller and the secondary display controller is configured to provide a secondary timing indication to the primary display controller; and
a processor coupled to the plurality of display controllers to receive a primary timing indication from the primary display controller;
wherein the primary display controller comprises a signal processor configured to implement an AND operation on the timing signals generated by one or more secondary display controllers, and
wherein the processor is configured to delay a refresh instruction until the primary timing indication is received from the primary display controller to synchronize the plurality of display panels.

### Claim 16 (depends on 15)

The device of claim 15, further comprising an application processor configured to generate image data to be rendered on the plurality of display panels of the device, wherein the signal processor is configured to synchronize the plurality of display panels when the application processor is not generating the image data.

### Claim 17 (depends on 15)

The device of claim 15, wherein the signal processor comprises a counter, the counter being configured to track a time elapsed since a last refresh.

### Claim 18 (depends on 15)

The device of claim 15, wherein implementing an AND operation on the timing signals generated by one or more secondary display controllers causes the primary timing indication to include both the primary timing indication and the one or more secondary timing indications.

### Claim 19 (depends on 15)

The device of claim 15, wherein the secondary timing indication is indicative of the secondary display controller residing in a state ready for refresh of a corresponding display panel and the primary timing indication is indicative of the first display controller residing in a state ready for refresh of a corresponding display and having received the secondary timing indication from the secondary display controller.

### Claim 20 (depends on 15)

The device of claim 15, further comprising the plurality of display panels, wherein the display controllers are each integrated with the respective display panels.