# US 11,308,912 B2 · Gate drive circuit for improving charging efficiency of display panel, display module and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,308,912 B2 - Document ID: US11308912B2 - Status: Granted - Kind: B2 - Application number: 17/164,068 - Filed: 2021-02-01 - Published: 2022-02-03 - Granted: 2022-04-19 - Earliest claimed: 2020-07-28 - Assignees: Beihai Hkc Optoelectronics Technology Co., Ltd.; Hkc Corporation Limited - Applicants: Beihai Hkc Optoelectronics Technology Co., Ltd.; Hkc Corporation Limited - Inventors: Chiayang Cheng; Chongwei Tang - Web page: https://patentgrep.com/patent/US11308912B2 ## CPC - G09G 3/3674: {Details of drivers for scan electrodes} - G09G 3/3688: {suitable for active matrices only} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0272: Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract A gate drive circuit includes: N array substrate row drive circuits arranged in cascade, an Nth array substrate row drive circuit is configured for outputting an Nth gate drive signal in response to a signal input terminal receiving a gate drive signal output by an N−1th array substrate row drive circuit to control Nth sub-pixels to charge; N auxiliary circuits, a timing signal input terminal is connected to an Nth timing control signal, a controlled terminal is connected to a pull-up control signal terminal of the N−1th array substrate row drive circuit, and an output terminal is connected to a gate drive signal output terminal; and the Nth auxiliary circuit is configured for controlling the Nth sub-pixels to charge in a determination that the Nth timing control signal connected to the timing signal input terminal and an N−1th pull-up control signal connected to the controlled terminal are both high level. ## Claims ### Claim 1 A gate drive circuit, comprising: N array substrate row drive circuits arranged in cascade, wherein each array substrate row drive circuit comprises a signal input terminal, a pull-up control signal terminal and a gate drive signal output terminal, and an Nth array substrate row drive circuit is configured for outputting an Nth gate drive signal in response to a signal input terminal of the Nth array substrate row drive circuit receiving a gate drive signal output by an (N−1)th array substrate row drive circuit to control Nth sub-pixels to charge; and N auxiliary circuits, wherein each auxiliary circuit is arranged corresponding to one of the N array substrate row drive circuits, and each auxiliary circuit comprises a timing signal input terminal, a controlled terminal and an output terminal, wherein: a timing signal input terminal of an Nth auxiliary circuit is connected to an Nth timing control signal, a controlled terminal of the Nth auxiliary circuit is connected to a pull-up control signal terminal of the (N−1)th array substrate row drive circuit, and an output terminal of the Nth auxiliary circuit is connected to a gate drive signal output terminal of the Nth array substrate row drive circuit; and the Nth auxiliary circuit is configured for controlling the Nth sub-pixels to charge in a determination that the Nth timing control signal connected to the timing signal input terminal of the Nth auxiliary circuit and an (N−1)th pull-up control signal connected to the controlled terminal of the Nth auxiliary circuit are both high level, wherein N is an integer and greater than 1. ### Claim 2 (depends on 1) The gate drive circuit of claim 1, wherein each auxiliary circuit comprises a first active switch, a controlled terminal of the first active switch is the controlled terminal of the each auxiliary circuit, an input terminal of the first active switch is the timing signal input terminal of the each auxiliary circuit, and an output terminal of the first active switch is the output terminal of the each auxiliary circuit. ### Claim 3 (depends on 1) The gate drive circuit of claim 1, wherein each array substrate row drive circuit comprises a charge circuit, a reset circuit and an output circuit, an input terminal of the charge circuit is the signal input terminal of the each array substrate row drive circuit, an output terminal of the charge circuit is the pull-up control signal terminal of the each array substrate row drive circuit and is connected to a controlled terminal of the output circuit, an input terminal of the output circuit is connected to a timing signal for the each array substrate row drive circuit, and an output terminal of the output circuit is the gate drive signal output terminal of the each array substrate row drive circuit. ### Claim 4 (depends on 1) A display module, comprising: a display panel; and the gate drive circuit as recited in claim 1, wherein the N array substrate row drive circuits arranged in cascade and the N auxiliary circuits are correspondingly arranged on at least one side of the display panel. ### Claim 5 (depends on 4) The display module of claim 4, wherein each auxiliary circuit comprises a first active switch, a controlled terminal of the first active switch is the controlled terminal of the each auxiliary circuit, an input terminal of the first active switch is the timing signal input terminal of the each auxiliary circuit, and an output terminal of the first active switch is the output terminal of the each auxiliary circuit. ### Claim 6 (depends on 5) The display module of claim 5, wherein each array substrate row drive circuit comprises a charge circuit, a reset circuit and an output circuit, an input terminal of the charge circuit is the signal input terminal of the each array substrate row drive circuit, an output terminal of the charge circuit is the pull-up control signal terminal of the each array substrate row drive circuit and is connected to a controlled terminal of the output circuit, an input terminal of the output circuit is connected to a current-level timing signal, and an output terminal of the output circuit is the gate drive signal output terminal of the each array substrate row drive circuit. ### Claim 7 (depends on 4) The display module of claim 4, comprising a first side and a second side arranged oppositely, wherein the N array substrate row drive circuits arranged in cascade and the N auxiliary circuits are both arranged on the first side and the second side. ### Claim 8 (depends on 7) The display module of claim 7, comprising a pixel array comprising odd-numbered rows of sub-pixels and even-numbered rows of sub-pixels, wherein: each odd-numbered row of sub-pixels is connected to one of the N array substrate row drive circuits arranged on the first side and one of the N auxiliary circuits arranged on the second side; and each even-numbered row of sub-pixels is connected to one of the N array substrate row drive circuits arranged on the second side and one of the N auxiliary circuits arranged on the first side. ### Claim 9 (depends on 8) The display module of claim 8, further comprising: a first substrate, comprising a display area and a non-display area, wherein the pixel array is arranged in the display area of the first substrate, and the N array substrate row drive circuits arranged in cascade and the N auxiliary circuits are arranged in the non-display area of the first substrate; a second substrate, arranged opposite to the first substrate; and a liquid crystal layer, arranged between the first substrate and the second substrate and comprising liquid crystal molecules, wherein the pixel array is configured for controlling actions of the liquid crystal molecules. ### Claim 10 (depends on 9) The display module of claim 9, further comprising a sealant arranged in a non-display area between the first substrate and the second substrate and surrounding the liquid crystal layer, wherein the N array substrate row drive circuits are located between the sealant and the display area. ### Claim 11 (depends on 9) The display module of claim 9, wherein the first substrate and the second substrate are both glass substrates or plastic substrates. ### Claim 12 (depends on 11) The display module of claim 11, wherein the first substrate is an array substrate, and the second substrate is a color filter substrate. ### Claim 13 (depends on 4) The display module of claim 4, comprising a first side and a second side arranged oppositely, wherein: the N array substrate row drive circuits arranged in cascade are all arranged on the first side; and the N auxiliary circuits are all arranged on the second side. ### Claim 14 (depends on 13) The display module of claim 13, comprising a pixel array comprising N rows of sub-pixels, wherein each row of sub-pixels is connected to one of the N array substrate row drive circuits and one of the N auxiliary circuits. ### Claim 15 (depends on 4) The display module of claim 4, further comprising a source drive circuit and data lines, wherein output terminals of the source drive circuit are connected to the pixel array of the display panel through the data lines. ### Claim 16 (depends on 15) The display module of claim 15, wherein the pixel array comprises a plurality of sub-pixels, each sub-pixel comprises three sub-pixels of red, green, and blue colors, gates of sub-pixels located in a same row are connected to an array substrate row drive circuit of a same level through a gate line, and sources of sub-pixels located in a same column are connected to the source drive circuit through one of the data lines. ### Claim 17 (depends on 4) The display module of claim 4, further comprising a timing controller and a driving power supply, wherein the timing controller is connected to the source drive circuit, and an output terminal of the driving power supply is connected to the N array substrate row drive circuits and the source drive circuit. ### Claim 18 (depends on 17) The display module of claim 17, wherein the sealant is coated on the first substrate or the second substrate. ### Claim 19 (depends on 4) A display device, comprising the display module as recited in claim 4. ### Claim 20 (depends on 1) A display device, comprising the gate drive circuit as recited in claim 1.