# US 11,308,911 B2 · Display device, driving method, and display system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,308,911 B2 - Document ID: US11308911B2 - Status: Granted - Kind: B2 - Application number: 17/042,892 - Filed: 2018-12-13 - Published: 2021-04-01 - Granted: 2022-04-19 - Earliest claimed: 2018-11-21 - Assignees: Hkc Corporation Limited - Applicants: Hkc Corporation Limited - Inventors: Xiaoyu Huang - Web page: https://patentgrep.com/patent/US11308911B2 ## CPC - G09G 3/3688: {suitable for active matrices only} - G09G 3/3677: {suitable for active matrices only} - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/02: Improving the quality of display appearance - G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes - G09G 2330/026: Arrangements or methods related to booting a display - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract This application discloses a display device, a driving method, and a display system. The display device includes the display panel, where the display panel includes a scanning line and a data line; a source driver chip arranged to output a source driver signal of the display panel and a gate driver chip arranged to output a gate driver signal of the display panel; a signal delay circuit, where the gate driver signal is output to the scanning line by the signal delay circuit; and the source driver signal is directly output to the data line. ## Claims ### Claim 1 A display device, comprising: a display panel, wherein the display panel comprises a scanning line and a data line; a source driver chip, configured to output a source driver signal of the display panel; a gate driver chip, configured to output a gate driver signal of the display panel; and a signal delay circuit, wherein the gate driver signal is output to the scanning line by the signal delay circuit; and the source driver signal is directly output to the data line; wherein the signal delay circuit comprises a D trigger, a resistor, a power supply, a ground line, a capacitor, and an active switch, a C end of the D trigger is connected to the resistor, another end of the resistor is connected to an output end of the gate driver chip, and a D end of the D trigger is connected to the power supply; an end of the capacitor is connected to the ground line, another end of the capacitor is connected to a control end of the active switch and a Q end of the D trigger, and the signal delay circuit further comprises a signal input end and a signal output end; and an output end of the gate driver chip is connected to the scanning line by the active switch. ### Claim 2 (depends on 1) The display device according to claim 1, wherein the active switch is a thin film transistor (TFT), and a gate of the TFT is connected to the capacitor, a source of the TFT is connected to the output end of the gate driver chip, and a drain of the TFT is connected to the scanning line. ### Claim 3 (depends on 1) The display device according to claim 1, wherein a charging time of the capacitor is longer than a display time of a frame of the display panel. ### Claim 4 (depends on 1) The display device according to claim 1, wherein a charging time of the capacitor is equal to a display time of a frame of the display panel. ### Claim 5 (depends on 1) The display device according to claim 1, wherein one scanning line corresponds to one signal delay circuit. ### Claim 6 (depends on 5) The display device according to claim 5, wherein there are at least two signal delay circuits, and delay time of the signal delay circuits is equal. ### Claim 7 (depends on 1) The display device according to claim 1, wherein the signal delay circuit is integrated into the gate driver chip. ### Claim 8 (depends on 1) The display device according to claim 1, wherein the display panel comprises a display area and a non-display area, the non-display area encloses the display area, the gate driver chip is connected to a first side of the non-display area, and the source driver chip is connected to a second side of the non-display area. ### Claim 9 A driving method for a display device, comprising steps of: outputting a gate driver signal to a scanning line by a signal delay circuit; and directly outputting a source driver signal to a data line; wherein the signal delay circuit comprises a D trigger, a resistor, a power supply, a ground line, a capacitor, and an active switch, a C end of the D trigger is connected to the resistor, another end of the resistor is connected to an output end of a gate driver chip of the display device, and a D end of the D trigger is connected to the power supply; an end of the capacitor is connected to the ground line, another end of the capacitor is connected to a control end of the active switch and a Q end of the D trigger, and the signal delay circuit further comprises a signal input end and a signal output end; and an output end of a gate driver chip of the display device is connected to the scanning line by the active switch. ### Claim 10 (depends on 9) The driving method for a display device according to claim 9, comprising: controlling a delay output time of a gate driver chip signal to be longer than a display time of a frame. ### Claim 11 (depends on 9) The driving method for a display device according to claim 9, comprising: controlling a delay output time of a gate driver chip signal to be equal to a display time of a frame. ### Claim 12 A display system, comprising a display device, wherein the display device comprises: a display panel, wherein the display panel comprises a scanning line and a data line; a source driver chip, configured to output a source driver signal of the display panel; a gate driver chip, configured to output a driver signal of the display panel; a signal delay circuit, wherein the gate driver signal is output to the scanning line by the signal delay circuit; and the source driver signal is directly output to the data line; and a backlight module, configured to provide a light source for the display device; wherein the signal delay circuit comprises a D trigger, a resistor, a power supply, a ground line, a capacitor, and an active switch, a C end of the D trigger is connected to the resistor, another end of the resistor is connected to an output end of the gate driver chip, and a D end of the D trigger is connected to the power supply; an end of the capacitor is connected to the ground line, another end of the capacitor is connected to a control end of the active switch and a Q end of the D trigger, and the signal delay circuit further comprises a signal input end and a signal output end; and an output end of the gate driver chip is connected to the scanning line by the active switch. ### Claim 13 (depends on 12) The display system according to claim 12, wherein a charging time of the capacitor is longer than or equal to a display time of a frame of the display panel. ### Claim 14 (depends on 12) The display system according to claim 12, wherein there are at least two scanning lines, and each scanning line corresponds to one signal delay circuit. ### Claim 15 (depends on 12) The display system according to claim 12, wherein the signal delay circuit is integrated into the gate driver chip. ### Claim 16 (depends on 12) The display system according to claim 12, wherein the display panel comprises a display area and a non-display area, the non-display area encloses the display area, the gate driver chip is connected to a first side of the non-display area, and the source driver chip is connected to a second side of the non-display area.