# US 11,308,909 B2 · Gate driver on array circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,308,909 B2 - Document ID: US11308909B2 - Status: Granted - Kind: B2 - Application number: 16/625,690 - Filed: 2019-11-18 - Published: 2021-10-28 - Granted: 2022-04-19 - Earliest claimed: 2019-10-14 - Assignees: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Inventors: Jiangchuan Chen - Web page: https://patentgrep.com/patent/US11308909B2 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3677: {suitable for active matrices only} - G09G 3/3266: Details of drivers for scan electrodes - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/043: Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/06: Details of flat display driving waveforms - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A gate driver on array (GOA) circuit, wherein each of GOA units includes a pull-up control circuit, wherein a control terminal thereof receives a first control signal, and a second terminal thereof outputs a second control signal; a pull-up circuit including a first transistor, wherein a control terminal thereof is connected to the second terminal of the pull-up control circuit, a first terminal thereof receives a first clock signal, and a second terminal thereof outputs a driving signal; a bootstrap capacitor connected between the second terminal of the pull-up control circuit and the second terminal of the first transistor; and a cascade-transmission circuit including a second transistor, wherein a control terminal thereof is connected to the second terminal of the pull-up control circuit, and a second terminal thereof outputs a cascade-transmission signal; wherein a duty cycle of the first clock signal is less than 33%. ## Claims ### Claim 1 A gate driver on array (GOA) circuit, comprising a plurality of cascaded GOA units, wherein each of the GOA units comprises: a pull-up control circuit, wherein a control terminal of the pull-up control circuit receives a first control signal, and a second terminal of the pull-up control circuit outputs a second control signal; a pull-up circuit comprising a first transistor, wherein a control terminal of the first transistor is connected to the second terminal of the pull-up control circuit, a first terminal of the first transistor receives a first clock signal, and a second terminal of the first transistor outputs a driving signal; a bootstrap capacitor connected between the second terminal of the pull-up control circuit and the second terminal of the first transistor; and a cascade-transmission circuit comprising a second transistor, wherein a control terminal of the second transistor is connected to the second terminal of the pull-up control circuit, a first terminal of the second transistor receives the first clock signal, and a second terminal of the second transistor outputs a cascade-transmission signal; wherein the first control signal is a cascade-transmission signal of a previous stage GOA unit or a start signal, and a duty cycle of the first clock signal is less than 33%, wherein the pull-up control circuit comprises: a third transistor; a fourth transistor, wherein a first terminal of the fourth transistor is connected to a second terminal of the third transistor, and a second terminal of the fourth transistor is connected to the control terminal of the first transistor; and a fifth transistor, wherein a control terminal of the fifth transistor is connected to the second terminal of the second transistor, a first terminal of the fifth transistor is connected to the first terminal of the fourth transistor, and a second terminal of the fifth transistor is connected to the second terminal of the second transistor, wherein each of the GOA units comprises a first pull-down circuit, and the first pull-down circuit comprises: a sixth transistor, wherein a control terminal of the sixth transistor receives a cascade-transmission signal of a next stage GOA unit, a first terminal of the sixth transistor is connected to the second terminal of the first transistor, and a second terminal of the sixth transistor is connected to a first low voltage terminal; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the sixth transistor, and a first terminal of the seventh transistor is connected to the second terminal of the pull-up control circuit and an eighth transistor, wherein a control terminal of the eighth transistor is connected to the control terminal of the seventh transistor, a first terminal of the eighth transistor is connected to a second terminal of the seventh transistor, and a second terminal of the eighth transistor is connected to a second low voltage terminal. ### Claim 2 (depends on 1) The GOA circuit as claimed in claim 1, wherein a first terminal of the pull-up control circuit is connected to the control terminal of the pull-up control circuit. ### Claim 3 (depends on 1) The GOA circuit as claimed in claim 1, wherein the first terminal of the eighth transistor is connected to the first terminal of the fifth transistor. ### Claim 4 (depends on 1) The GOA circuit as claimed in claim 1, wherein each of the GOA units comprises a second pull-down circuit, and the second pull-down circuit comprises: a ninth transistor, wherein a control terminal of the ninth transistor is connected to an output terminal of an inverter circuit, a first terminal of the ninth transistor is connected to the second terminal of the first transistor, and a second terminal of the ninth transistor is connected to the first low voltage terminal; a tenth transistor, wherein a control terminal of the tenth transistor is connected to the control terminal of the ninth transistor, and a first terminal of the tenth transistor is connected to the second terminal of the pull-up control circuit; and an eleventh transistor, wherein a control terminal of the eleventh transistor is connected to the control terminal of the tenth transistor, a first terminal of the eleventh transistor is connected to a second terminal of the tenth transistor, and a second terminal of the eleventh transistor is connected to the second low voltage terminal. ### Claim 5 (depends on 4) The GOA circuit as claimed in claim 4, wherein the first terminal of the eleventh transistor is connected to the first terminal of the fifth transistor. ### Claim 6 (depends on 4) The GOA circuit as claimed in claim 4, wherein the inverter circuit comprises: a twelfth transistor; a thirteenth transistor, wherein a control terminal of the thirteenth transistor is connected to a second terminal of the twelfth transistor, a first terminal of the thirteenth transistor receives a second clock signal, and a second terminal of the thirteenth transistor is connected to the control terminal of the ninth transistor; a fourteenth transistor, wherein a control terminal of the fourteenth transistor receives the first clock signal, a first terminal of the fourteenth transistor is connected to the second terminal of the twelfth transistor, and a second terminal of the fourteenth transistor is connected to the second low voltage terminal; and a fifteenth transistor, wherein a control terminal of the fifteenth transistor receives the first clock signal, a first terminal of the fifteenth transistor is connected to the second terminal of the thirteenth transistor, and a second terminal of the fifteenth transistor is connected to the second low voltage terminal. ### Claim 7 (depends on 6) The GOA circuit as claimed in claim 6, wherein a control terminal and a first terminal of the twelfth transistor receive the second clock signal. ### Claim 8 (depends on 7) The GOA circuit as claimed in claim 7, wherein a delay time of the second clock signal relative to the first clock signal is greater than a time when the first clock signal or the second clock signal is at a high voltage level during a clock cycle time. ### Claim 9 A gate driver on array (GOA) circuit, comprising a plurality of cascaded GOA units, wherein each of the GOA units comprises: a pull-up control circuit, wherein a control terminal of the pull-up control circuit receives a first control signal, a first terminal of the pull-up control circuit is connected to the control terminal of the pull-up control circuit, and a second terminal of the pull-up control circuit outputs a second control signal; a pull-up circuit comprising a first transistor, wherein a control terminal of the first transistor is connected to the second terminal of the pull-up control circuit, a first terminal of the first transistor receives a first clock signal, and a second terminal of the first transistor outputs a driving signal; a bootstrap capacitor connected between the second terminal of the pull-up control circuit and the second terminal of the first transistor; and a cascade-transmission circuit comprising a second transistor, wherein a control terminal of the second transistor is connected to the second terminal of the pull-up control circuit, a first terminal of the second transistor receives the first clock signal, and a second terminal of the second transistor outputs a cascade-transmission signal; wherein the first control signal is a cascade-transmission signal of a previous stage GOA unit or a start signal, and a duty cycle of the first clock signal is less than 33%, wherein the pull-up control circuit comprises: a third transistor; a fourth transistor, wherein a first terminal of the fourth transistor is connected to a second terminal of the third transistor, and a second terminal of the fourth transistor is connected to the control terminal of the first transistor; and a fifth transistor, wherein a control terminal of the fifth transistor is connected to the second terminal of the second transistor, a first terminal of the fifth transistor is connected to the first terminal of the fourth transistor, and a second terminal of the fifth transistor is connected to the second terminal of the second transistor wherein each of the GOA units comprises a first pull-down circuit, and the first pull-down circuit comprises: a sixth transistor, wherein a control terminal of the sixth transistor receives a cascade-transmission signal of a next stage GOA unit, a first terminal of the sixth transistor is connected to the second terminal of the first transistor, and a second terminal of the sixth transistor is connected to a first low voltage terminal; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the sixth transistor, and a first terminal of the seventh transistor is connected to the second terminal of the pull-up control circuit and an eighth transistor, wherein a control terminal of the eighth transistor is connected to the control terminal of the seventh transistor, a first terminal of the eighth transistor is connected to a second terminal of the seventh transistor, and a second terminal of the eighth transistor is connected to a second low voltage terminal. ### Claim 10 (depends on 9) The GOA circuit as claimed in claim 9, wherein the first terminal of the eighth transistor is connected to the first terminal of the fifth transistor. ### Claim 11 (depends on 9) The GOA circuit as claimed in claim 9, wherein each of the GOA units comprises a second pull-down circuit, and the second pull-down circuit comprises: a ninth transistor, wherein a control terminal of the ninth transistor is connected to an output terminal of an inverter circuit, a first terminal of the ninth transistor is connected to the second terminal of the first transistor, and a second terminal of the ninth transistor is connected to the first low voltage terminal; a tenth transistor, wherein a control terminal of the tenth transistor is connected to the control terminal of the ninth transistor, and a first terminal of the tenth transistor is connected to the second terminal of the pull-up control circuit; and an eleventh transistor, wherein a control terminal of the eleventh transistor is connected to the control terminal of the tenth transistor, a first terminal of the eleventh transistor is connected to a second terminal of the tenth transistor, and a second terminal of the eleventh transistor is connected to the second low voltage terminal. ### Claim 12 (depends on 11) The GOA circuit as claimed in claim 11, wherein the first terminal of the eleventh transistor is connected to the first terminal of the fifth transistor. ### Claim 13 (depends on 11) The GOA circuit as claimed in claim 11, wherein the inverter circuit comprises: a twelfth transistor; a thirteenth transistor, wherein a control terminal of the thirteenth transistor is connected to a second terminal of the twelfth transistor, a first terminal of the thirteenth transistor receives a second clock signal, and a second terminal of the thirteenth transistor is connected to the control terminal of the ninth transistor; a fourteenth transistor, wherein a control terminal of the fourteenth transistor receives the first clock signal, a first terminal of the fourteenth transistor is connected to the second terminal of the twelfth transistor, and a second terminal of the fourteenth transistor is connected to the second low voltage terminal; and a fifteenth transistor, wherein a control terminal of the fifteenth transistor receives the first clock signal, a first terminal of the fifteenth transistor is connected to the second terminal of the thirteenth transistor, and a second terminal of the fifteenth transistor is connected to the second low voltage terminal. ### Claim 14 (depends on 13) The GOA circuit as claimed in claim 13, wherein a control terminal and a first terminal of the twelfth transistor receive the second clock signal. ### Claim 15 (depends on 14) The GOA circuit as claimed in claim 14, wherein a delay time of the second clock signal relative to the first clock signal is greater than a time when the first clock signal or the second clock signal is at a high voltage level during a clock cycle time.