# US 11,308,907 B2 · Shift register and driving method of shift register, gate driving circuit and display panel and device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,308,907 B2 - Document ID: US11308907B2 - Status: Granted - Kind: B2 - Application number: 17/138,925 - Filed: 2020-12-31 - Published: 2021-04-22 - Granted: 2022-04-19 - Earliest claimed: 2020-11-16 - Assignees: Shanghai Tianma Am-Oled Co., Ltd. - Applicants: Shanghai Tianma Am-Oled Co., Ltd. - Inventors: Mengmeng Zhang; Xingyao Zhou - Web page: https://patentgrep.com/patent/US11308907B2 ## CPC - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3655: {Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors} - G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element - G09G 3/3677: {suitable for active matrices only} - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0214: with crosstalk due to leakage current of pixel switch in active matrix panels - G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Provided are a shift register and a driving method of a shift register, a gate driving circuit and a display panel and device. The shift register includes a first power signal input terminal, a second power signal input terminal, a first signal output terminal, a first node control device, a first output device, a first voltage stabilizing device and a first clock signal terminal, where a first terminal of the first voltage stabilizing device is electrically connected to an output terminal of the first node control device at a first node, a second terminal of the first voltage stabilizing device is electrically connected to a first control terminal of the first output device at a second node, and a control terminal of the first voltage stabilizing device is electrically connected to the first clock signal terminal. ## Claims ### Claim 1 A shift register, comprising: a first power signal input terminal, a second power signal input terminal, a first signal output terminal, a first node control device, a first output device, a first voltage stabilizing device and a first clock signal terminal; wherein a first terminal of the first voltage stabilizing device is electrically connected to an output terminal of the first node control device at a first node, a second terminal of the first voltage stabilizing device is electrically connected to a first control terminal of the first output device at a second node, and a control terminal of the first voltage stabilizing device is electrically connected to the first clock signal terminal; a first input terminal of the first output device is electrically connected to the first power signal input terminal, a second input terminal of the first output device is electrically connected to the second power signal input terminal, and an output terminal of the first output device is electrically connected to the first signal output terminal; in a display stage of a first frequency, the first voltage stabilizing device is configured to be turned on according to a control signal provided by the first clock signal terminal; or in a display stage of a second frequency, the first voltage stabilizing device is configured to be turned on or turned off according to a control signal provided by the first clock signal terminal; wherein the first frequency is greater than the second frequency; and wherein the display stage of the second frequency comprises a first sub-stage and a second sub-stage, and the first sub-stage corresponds to an initialization stage and a data signal writing stage of a pixel circuit, and the second sub-stage corresponds to a light emission stage of the pixel circuit; wherein in the first sub-stage, the first voltage stabilizing device is configured to be turned on according to the control signal provided by the first clock signal terminal; and in the second sub-stage, the first voltage stabilizing device is configured to be turned off according to the control signal provided by the first clock signal terminal. ### Claim 2 (depends on 1) The shift register according to claim 1, further comprising: a second node control device and a second clock signal terminal; wherein a first input terminal of the second node control device is electrically connected to the second power signal input terminal, a first control terminal of the second node control device is electrically connected to the first node, and an output terminal of the second node control device is electrically connected to a second control terminal of the first output device; a first input terminal of the first node control device is electrically connected to the first power signal input terminal, and a first control terminal of the first node control device is electrically connected to the second clock signal terminal; and in a low level output stage of the first signal output terminal, a low level signal is input into the second clock signal terminal. ### Claim 3 (depends on 2) The shift register according to claim 2, further comprising: a second signal output terminal; wherein a second input terminal of the first node control device is electrically connected to the second power signal input terminal, and a second control terminal of the first node control device is electrically connected to the second signal output terminal; and wherein the first node control device comprises a first transistor, a second transistor and a third transistor, wherein a first electrode of the first transistor is the first input terminal of the first node control device, a gate of the first transistor is the first control terminal of the first node control device, a first electrode of the second transistor is the second input terminal of the first node control device, a gate of the second transistor and a gate of the third transistor are electrically connected to each other to be the second control terminal of the first node control device, a second electrode of the second transistor is electrically connected to a first electrode of the third transistor, and a second electrode of the third transistor and a second electrode of the first transistor are electrically connected to each other to be the output terminal of the first node control device. ### Claim 4 (depends on 3) The shift register according to claim 3, wherein the first terminal of the first voltage stabilizing device is electrically connected to the second electrode of the first transistor, and the second terminal of the first voltage stabilizing device is electrically connected to the second node. ### Claim 5 (depends on 3) The shift register according to claim 3, wherein the first node control device further comprises a fourth transistor, wherein a first electrode of the fourth transistor is electrically connected to the second electrode of the first transistor, a second electrode of the fourth transistor serves as the output terminal of the first node control device to be electrically connected to the first terminal of the first voltage stabilizing device, and the second terminal of the first voltage stabilizing device is electrically connected to the second node; or the first terminal of the first voltage stabilizing device is electrically connected to the second electrode of the first transistor, the second terminal of the first voltage stabilizing device is electrically connected to a first electrode of the fourth transistor, and a second electrode of the fourth transistor is electrically connected to the second node; and a gate of the fourth transistor is electrically connected to the first power signal input terminal. ### Claim 6 (depends on 1) The shift register according to claim 1, further comprising: a third node control device, a fourth node control device, a second output device, a storage device, a coupling device, a shift register signal input terminal, a third clock signal terminal, a fourth clock signal terminal and a second signal output terminal; wherein a first input terminal of the third node control device is electrically connected to the second power signal input terminal, a second input terminal of the third node control device is electrically connected to the shift register signal input terminal, a first control terminal of the third node control device, an output terminal of the fourth node control device, a first control terminal of the second output device and a first terminal of the storage device are electrically connected at a third node, a second control terminal of the third node control device is electrically connected to the third clock signal terminal, a third control terminal of the third node control device is electrically connected to the fourth clock signal terminal, and an output terminal of the third node control device, a first control terminal of the fourth node control device and a second control terminal of the second output device are electrically connected at a fourth node; a first input terminal of the fourth node control device is electrically connected to the shift register signal input terminal, a second input terminal of the fourth node control device is electrically connected to the first power signal input terminal, and a second control terminal of the fourth node control device is electrically connected to the third clock signal terminal; a first input terminal of the second output device is electrically connected to the second power signal input terminal, a second input terminal of the second output device is electrically connected to the fourth clock signal terminal, and an output terminal of the second output device is electrically connected to the second signal output terminal; a second terminal of the storage device is electrically connected to the second power signal input terminal; and a first terminal of the coupling device is electrically connected to the second node, and a second terminal of the coupling device is electrically connected to the first signal output terminal. ### Claim 7 (depends on 1) The shift register according to claim 1, further comprising: a third node control device, a second voltage stabilizing device, a second output device, a second signal output terminal and a fifth clock signal terminal; wherein a first input terminal of the third node control device is electrically connected to the second power signal input terminal, a first control terminal of the third node control device is electrically connected to a first terminal of the second voltage stabilizing device at a third node, a second terminal of the second voltage stabilizing device is electrically connected to the first control terminal of the first output device, and a control terminal of the second voltage stabilizing device is electrically connected to the fifth clock signal terminal; and in the display stage of the first frequency, the second voltage stabilizing device is configured to be turned on according to a control signal provided by the fifth clock signal terminal; in the display stage of the second frequency, the second voltage stabilizing device is configured to be turned on or turned off according to a control signal provided by the fifth clock signal terminal. ### Claim 8 (depends on 7) The shift register according to claim 7, wherein the display stage of the second frequency comprises a first sub-stage and a second sub-stage, and the first sub-stage corresponds to an initialization stage and a data signal writing stage of a pixel circuit; wherein in the first sub-stage, the second voltage stabilizing device is configured to be turned on according to the control signal provided by the fifth clock signal terminal; in the second sub-stage, the second voltage stabilizing device is configured to be turned off according to the control signal provided by the fifth clock signal terminal. ### Claim 9 (depends on 7) The shift register according to claim 7, further comprising: a fourth node control device, a shift register signal input terminal, a third clock signal terminal and a fourth clock signal terminal; wherein a second input terminal of the third node control device is electrically connected to the shift register signal input terminal, a second control terminal of the third node control device is electrically connected to the third clock signal terminal, a third control terminal of the third node control device is electrically connected to the fourth clock signal terminal, an output terminal of the third node control device, a first control terminal of the fourth node control device and a second control terminal of the first output device are electrically connected at a fourth node, a first input terminal of the fourth node control device is electrically connected to the shift register signal input terminal, a second input terminal of the fourth node control device is electrically connected to the first power signal input terminal, a second control terminal of the fourth node control device is electrically connected to the third clock signal terminal, and an output terminal of the fourth node control device is electrically connected to the third node; the first input terminal of the first output device is electrically connected to the second power signal input terminal, the second input terminal of the first output device is electrically connected to the fourth clock signal terminal, and the output terminal of the first output device is electrically connected to the second signal output terminal; and in a high level output stage of the second signal output terminal, a high level signal is input into both of the third clock signal terminal and the fourth clock signal terminal. ### Claim 10 (depends on 9) The shift register according to claim 9, further comprising: a third voltage stabilizing device and a sixth clock signal terminal, wherein a first terminal of the third voltage stabilizing device is electrically connected to the output terminal of the third node control device, a second terminal of the third voltage stabilizing device is electrically connected to a second control terminal of the second output device, and a control terminal of the third voltage stabilizing device is electrically connected to the sixth clock signal terminal; and in the display stage of the first frequency, the third voltage stabilizing device is configured to be turned on according to a control signal provided by the sixth clock signal terminal; or in the display stage of the second frequency, the third voltage stabilizing device is configured to be turned on or turned off according to a control signal provided by the sixth clock signal terminal. ### Claim 11 (depends on 10) The shift register according to claim 10, wherein the display stage of the second frequency comprises a first sub-stage and a second sub-stage, and the first sub-stage corresponds to an initialization stage and a data signal writing stage of a pixel circuit; in the first sub-stage, the third voltage stabilizing device is configured to be turned on according to the control signal provided by the sixth clock signal terminal; in the second sub-stage, the third voltage stabilizing device is configured to be turned off according to the control signal provided by the sixth clock signal terminal. ### Claim 12 (depends on 10) The shift register according to claim 10, wherein the third node control device comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; wherein a first electrode of the fifth transistor is the first input terminal of the third node control device, a gate of the fifth transistor is the first control terminal of the third node control device, a second electrode of the fifth transistor is electrically connected to a first electrode of the sixth transistor, a gate of the sixth transistor is the third control terminal of the third node control device, a second electrode of the sixth transistor is electrically connected to a first electrode of the seventh transistor to serve as the output terminal of the third node control device, a second electrode of the seventh transistor is electrically connected to a first electrode of the eighth transistor, a second electrode of the eighth transistor is the second input terminal of the third node control device, and a gate of the seventh transistor and a gate of the eighth transistor are electrically connected to each other to be the second control terminal of the third node control device, wherein the first terminal of the third voltage stabilizing device is electrically connected to the second electrode of the sixth transistor, and the second terminal of the third voltage stabilizing device is electrically connected to the second control terminal of the second output device. ### Claim 13 (depends on 12) The shift register according to claim 12, wherein the third node control device further comprises a ninth transistor, wherein a first electrode of the ninth transistor is electrically connected to the second electrode of the sixth transistor, a second electrode of the ninth transistor serves as the output terminal of the third node control device to be electrically connected to the first terminal of the third voltage stabilizing device, and the second terminal of the third voltage stabilizing device is electrically connected to the second control terminal of the second output device; or the first terminal of the third voltage stabilizing device is electrically connected to the second electrode of the sixth transistor, the second terminal of the third voltage stabilizing device is electrically connected to a first electrode of the ninth transistor, and a second electrode of the ninth transistor is electrically connected to the second control terminal of the second output device; and a gate of the ninth transistor is electrically connected to the first power signal input terminal. ### Claim 14 (depends on 7) The shift register according to claim 7, further comprising: a storage device and a coupling device; wherein a first terminal of the storage device is electrically connected to the third node, and a second terminal of the storage device is electrically connected to the second power signal input terminal; and a first terminal of the coupling device is electrically connected to the second node, and a second terminal of the coupling device is electrically connected to the first signal output terminal. ### Claim 15 (depends on 10) The shift register according to claim 10, wherein the first voltage stabilizing device comprises a first voltage stabilizing transistor, a first electrode of the first voltage stabilizing transistor is the first terminal of the first voltage stabilizing device, a second electrode of the first voltage stabilizing transistor is the second terminal of the first voltage stabilizing device, and a gate of the first voltage stabilizing transistor is the control terminal of the first voltage stabilizing device; the second voltage stabilizing device comprises a second voltage stabilizing transistor, a first electrode of the second voltage stabilizing transistor is the first terminal of the second voltage stabilizing device, a second electrode of the second voltage stabilizing transistor is the second terminal of the second voltage stabilizing device, and a gate of the second voltage stabilizing transistor is the control terminal of the second voltage stabilizing device; the third voltage stabilizing device comprises a third voltage stabilizing transistor, a first electrode of the third voltage stabilizing transistor is the first terminal of the third voltage stabilizing device, a second electrode of the third voltage stabilizing transistor is the second terminal of the third voltage stabilizing device, and a gate of the third voltage stabilizing transistor is the control terminal of the third voltage stabilizing device; and each of the first voltage stabilizing transistor, the second voltage stabilizing transistor and the third voltage stabilizing transistor is an oxide semiconductor transistor; wherein the first clock signal terminal, the fifth clock signal terminal, and the sixth clock signal terminal have a same clock signal. ### Claim 16 (depends on 1) A driving method of a shift register, which is applied for driving the shift register according to claim 1, comprising: in the display stage of the first frequency, controlling, by a control signal of the first clock signal terminal, the first voltage stabilizing device to be turned on; in the display stage of the second frequency, controlling, by a control signal of the first clock signal terminal, the first voltage stabilizing device to be turned on or turned off; wherein the first frequency is greater than the second frequency. ### Claim 17 (depends on 16) The driving method according to claim 16, wherein the display stage of the second frequency comprises a first sub-stage and a second sub-stage, and the first sub-stage corresponds to an initialization stage and a data signal writing stage of a pixel circuit; and wherein in the display stage of the second frequency, controlling, by the control signal of the first clock signal terminal, the first voltage stabilizing device to be turned on or turned off comprises: in the first sub-stage, controlling, by the control signal provided by the first clock signal terminal, the first voltage stabilizing device to be turned on; in the second sub-stage, controlling, by the control signal provided by the first clock signal terminal, the first voltage stabilizing device to be turned off. ### Claim 18 (depends on 16) The driving method according to claim 16, wherein the shift register further comprises a third node control device, a second voltage stabilizing device, a second output device, a second signal output terminal and a fifth clock signal terminal; wherein a first input terminal of the third node control device is electrically connected to the second power signal input terminal, a first control terminal of the third node control device is electrically connected to a first terminal of the second voltage stabilizing device at a third node, a second terminal of the second voltage stabilizing device is electrically connected to the first control terminal of the first output device, and a control terminal of the second voltage stabilizing device is electrically connected to the fifth clock signal terminal; and wherein the driving method further comprises: in the display stage of the first frequency, controlling, by the control signal of the fifth clock signal terminal, the second voltage stabilizing device to be turned on; in the display stage of the second frequency, controlling, by the control signal of the fifth clock signal terminal, the second voltage stabilizing device to be turned on or turned off. ### Claim 19 (depends on 18) The driving method according to claim 18, wherein the display stage of the second frequency comprises a first sub-stage and a second sub-stage, and the first sub-stage corresponds to an initialization stage and a data signal writing stage of a pixel circuit; and wherein in the display stage of the second frequency, controlling, by the control signal of the fifth clock signal terminal, the second voltage stabilizing device to be turned on or turned off comprises: in the first sub-stage, controlling, by the control signal of the fifth clock signal terminal, the second voltage stabilizing device to be turned on; in the second sub-stage, controlling, by the control signal of the fifth clock signal terminal, the second voltage stabilizing device to be turned off. ### Claim 20 (depends on 1) A gate driving circuit, comprising: cascaded shift registers according to claim 1; wherein a shift register signal input terminal of the shift register at a first level is electrically connected to an initial signal input terminal of the gate driving circuit, and the first signal output terminal of the shift register at an i-th level is electrically connected to a shift register signal input terminal of the shift register at an (i+1)-th level; wherein i is a positive integer. ### Claim 21 (depends on 20) A display panel, comprising: a display region and a non-display region surrounding the display region, wherein the non-display region is provided with a gate driving circuit, and the gate driving circuit is the gate driving circuit according to claim 20; and wherein the display region is provided with a plurality of scanning lines and a plurality of data lines, the plurality of scanning lines and the plurality of data lines are intersected to define a plurality of sub-pixel regions, and each of the plurality of sub-pixel regions is provided with a pixel circuit; wherein the pixel circuit comprises at least one N-type transistor and at least one P-type transistor; and in each row of pixel circuits, a control terminal of the at least one N-type transistor is electrically connected to the first signal output terminal of the shift register at one level through one scanning line, and a control terminal of the at least one P-type transistor is electrically connected to a second signal output terminal of the shift register at the one level through another scanning line; the display panel can be used in a display device.