# US 11,308,885 B2 · Display panel for outputting a same gate signal to two pixels on different lines and driving method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,308,885 B2 - Document ID: US11308885B2 - Status: Granted - Kind: B2 - Application number: 16/618,894 - Filed: 2019-06-28 - Published: 2021-10-21 - Granted: 2022-04-19 - Earliest claimed: 2018-08-08 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Tian Dong - Web page: https://patentgrep.com/patent/US11308885B2 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3225: using an active matrix - G09G 3/3275: Details of drivers for data electrodes - G09G 2300/043: Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0205: Simultaneous scanning of several lines in flat panels - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract The disclosure relates to a display panel. The display panel may include a pixel unit group and a scanning circuit. The pixel unit group may include a first pixel unit and a second pixel unit. The scanning circuit may include a first scan signal terminal and a second scan signal terminal. The first scan signal terminal may be configured to simultaneously provide a same gate signal to the first pixel unit and the second pixel unit, and/or the second scan signal terminal may be configured to simultaneously provide a same light emitting control signal to the first pixel unit and the second pixel unit. ## Claims ### Claim 1 A display panel, comprising: a pixel unit group, the pixel unit group comprising a first pixel unit and a second pixel unit, the first pixel unit and the second pixel unit respectively comprising a first pixel circuit and a second pixel circuit, the first pixel circuit comprising a first gate control terminal and a first light emitting control terminal, and the second pixel circuit comprising a second gate control terminal and a second light emitting control terminal; a scanning circuit, the scanning circuit comprising a first scan signal terminal and a second scan signal terminal; and a first data line and a second data line; wherein the first scan signal terminal is configured to simultaneously provide a same gate signal to the first pixel unit and the second pixel unit, and/or the second scan signal terminal is configured to simultaneously provide a same light emitting control signal to the first pixel unit and the second pixel unit; the first data line is connected to the first pixel circuit, and the second data line is connected to the second pixel circuit; the display panel is configured to simultaneously provide the same gate signal to the first gate control terminal and the second gate control terminal during a first period using the first scan signal terminal of the scanning circuit, and the first period includes a first sub-period and a second sub-period in sequence; and the display panel is further configured to write a first data signal to the first pixel circuit through the first data line and a second data signal to the second pixel circuit through the second data line during the first sub-period. ### Claim 2 (depends on 1) The display panel of claim 1, further comprising: at least one gate line, wherein the first scan signal terminal is connected to the first gate control terminal and the second gate control terminal through the at least one gate line, and simultaneously provide the same gate signal to the first pixel unit and the second pixel unit through the at least one gate line. ### Claim 3 (depends on 2) The display panel of claim 2, further comprising: at least one light emitting control line, wherein the second scan signal terminal is connected to the first light emitting control terminal and the second light emitting control terminal through the at least one light emitting control line, and simultaneously provide the same light emitting control signal to the first pixel unit and the second pixel unit. ### Claim 4 (depends on 1) The display panel of claim 1, further comprising a multiplexing circuit and a data driving circuit, wherein the data driving circuit comprises a first data signal output terminal, the multiplexing circuit is connected to the first data signal output terminal, the first data line and the second data line, and is configured to electrically connect the first data signal output terminal to the first data line and the second data line in a time-multiplexing manner. ### Claim 5 (depends on 4) The display panel of claim 4, wherein the multiplexing circuit comprises a first selection circuit and a second selection circuit, a first terminal of the first selection circuit is connected to the first data line, a first terminal of the second selection circuit is connected to the second data line, and second terminals of both the first selection circuit and the second selection circuit are connected to the first data signal output terminal. ### Claim 6 (depends on 5) The display panel of claim 5, wherein the first selection circuit comprises a first multiplexing transistor, and the second selection circuit comprises a second multiplexing transistor; a first terminal and a second terminal of the first multiplexing transistor are respectively configured as the first terminal and the second terminal of the first selection circuit, and a first terminal and a second terminal of the second multiplexing transistor are respectively configured as the first terminal and the second terminal of the second selection circuit. ### Claim 7 (depends on 6) The display panel of claim 6, wherein a control terminal of the first multiplexing transistor and a control terminal of the second multiplexing transistor are configured to receive a same multiplexing control signal. ### Claim 8 (depends on 7) The display panel of claim 7, wherein the first multiplexing transistor and the second multiplexing transistor are of opposite types. ### Claim 9 (depends on 7) The display panel of claim 7, wherein the first multiplexing transistor and the second multiplexing transistor are of the same type. ### Claim 10 (depends on 7) The display panel according to claim 7, wherein the multiplexing circuit further comprises a multiplexing signal generating circuit, and the multiplexing signal generating circuit is configured to provide the same or inverted multiplexing control signal to the control terminals of the first multiplexing transistor and the second multiplexing transistor. ### Claim 11 (depends on 6) The display panel of claim 6, wherein a control terminal of the first multiplexing transistor and a control terminal of the second multiplexing transistor are configured to respectively receive a first multiplexing control signal and a second multiplexing control signal that are inverted from each other, and the first multiplexing transistor and the second multiplexing transistor are of the same type. ### Claim 12 (depends on 1) The display panel according to claim 1, wherein the scanning circuit comprises a first scanning sub-circuit and a second scanning sub-circuit, the first scanning sub-circuit comprises the first scan signal terminal, and the second scanning sub-circuit comprises the second scan signal terminal. ### Claim 13 (depends on 12) The display panel of claim 12, wherein the first scan sub-circuit comprises a first shift register unit which is configured to be cascaded and comprise the first scan signal terminal, and the second scan sub-circuit comprises a second shift register unit which is configured to be cascaded and comprise the second scan signal terminal. ### Claim 14 (depends on 1) A display apparatus, comprising the display panel of claim 1. ### Claim 15 (depends on 1) The display panel of claim 1, wherein to write the first data signal to the first pixel circuit through the first data line and the second data signal to the second pixel circuit through the second data line during the first sub-period comprises: to write the first data signal to the first data line during a first write period and writing the first data signal to the first pixel circuit during the first sub-period; and to write the second data signal to the second data line during a second write period and writing the second data signal to the second pixel circuit during the first sub-period. ### Claim 16 (depends on 15) The display panel of claim 15, wherein, the first write period is located before the first sub-period and is temporally adjacent to the first sub-period, and the second write period is located in the first sub-period; or the second write period is located before the first sub-period and is temporally adjacent to the first sub-period, and the first write period is located before the second write period and is temporally adjacent to the second write period. ### Claim 17 (depends on 1) The display panel of claim 1, wherein the display panel is further configured to provide simultaneously the same light emitting control signal to the first light emitting control terminal and the second light emitting control terminal using the second scan signal terminal of the scanning circuit in a second period. ### Claim 18 (depends on 17) The display panel of claim 17, wherein the display panel further comprises a multiplexing circuit and a data driving circuit, the data driving circuit comprising a first data signal output terminal, the display panel is further configured: to connect the first data line to the first data signal output terminal during the first write period to write the first data signal to the first data line; and to connect the second data line to the second data signal output terminal during the second write period to write the second data signal to the second data line.