# US 11,308,876 B2 · Pixel driving circuit, driving method thereof and display device

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- Number: US 11,308,876 B2
- Document ID: US11308876B2
- Status: Granted
- Kind: B2
- Application number: 16/491,547
- Filed: 2019-03-28
- Published: 2021-11-25
- Granted: 2022-04-19
- Earliest claimed: 2018-05-21
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.
- Inventors: Dongni Liu; Minghua Xuan; Xiaochuan Chen; Lei Wang; Zheng Fang; Li Xiao; Liang Chen; Shengji Yang; Pengcheng Lu
- Web page: https://patentgrep.com/patent/US11308876B2

## CPC

- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/3275: Details of drivers for data electrodes
- G09G 2300/0421: Structural details of the set of electrodes
- G09G 2300/0809: Several active elements per pixel in active matrix panels
- G09G 2300/0814: used for selection purposes, e.g. logical AND for partial update
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2300/0866: by means of changes in the pixel supply voltage
- G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2320/0257: Reduction of after-image effects
- G09G 2330/02: Details of power systems and of start or stop of display operation
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A pixel driving circuit including: N pixel circuits each including a first node and a power supply terminal, N being an integer greater than 1; and N multiplexing circuits configured to selectively couple a data line to the first nodes of the N pixel circuits. A first one of the N multiplexing circuits includes a multiplexing control circuit, and a second one to an N-th one of the N multiplexing circuits include respective multiplexing control circuits and respective reset circuits. The reset circuit of a (j+1)-th one of the N multiplexing circuits is configured to reset the first node of a (j+1)-th one of the N pixel circuits with a power supply voltage in response to a j-th multiplexing control signal being active, j being an integer and 1≤j<N.

## Claims

### Claim 1

A pixel driving circuit, comprising:
N pixel circuits, each of the pixel circuits comprising a first node and a power supply terminal, the first node configured to receive a data voltage, the power supply terminal configured to receive a power supply voltage, wherein N is an integer greater than 1; and
N multiplexing circuits configured to selectively couple a data line to the first nodes of the N pixel circuits, wherein a first one of the N multiplexing circuits comprises a multiplexing control circuit, and a second one to an N-th one of the N multiplexing circuits comprise respective multiplexing control circuits and respective reset circuits, wherein
the multiplexing control circuit of an i-th one of the N multiplexing circuits is configured to couple the data line to the first node of an i-th one of the N pixel circuits in response to an i-th multiplexing control signal being active, i being an integer and 1≤i≤N, and
the reset circuit of a (j+1)-th one of the N multiplexing circuits is configured to reset the first node of a (j+1)-th one of the N pixel circuits with the power supply voltage in response to a j-th multiplexing control signal being active, j being an integer and 1≤j<N.

### Claim 2 (depends on 1)

The pixel driving circuit of claim 1, wherein the multiplexing control circuits of the N multiplexing circuits are configured such that the data line is sequentially coupled to the first nodes of the N pixel circuits.

### Claim 3 (depends on 1)

The pixel driving circuit of claim 1, wherein the multiplexing control circuit of the i-th one of the N multiplexing circuits comprises a first transistor comprising:
a control electrode configured to receive the i-th multiplexing control signal;
a first electrode connected to the data line; and
a second electrode connected to the first node of the i-th one of the N pixel circuits.

### Claim 4 (depends on 1)

The pixel driving circuit of claim 1, wherein the reset circuit of the (j+1)-th one of the N multiplexing circuits comprises a second transistor comprising:
a control electrode configured to receive the j-th multiplexing control signal;
a first electrode connected to the first node of the (j+1)-th one of the N pixel circuits; and
a second electrode connected to the power supply terminal of the (j+1)-th one of the N pixel circuits.

### Claim 5 (depends on 1)

The pixel driving circuit of claim 1, wherein each of the N pixel circuits comprises a compensation sub-circuit, a driving sub-circuit, a light emission control sub-circuit, a reset sub-circuit, and a light emission sub-circuit, wherein
the reset sub-circuit is configured to reset the driving sub-circuit and the light emission sub-circuit with a reset voltage in response to a first scan signal being active during a reset phase,
the compensation sub-circuit is configured to transfer the data voltage at the first node to the driving sub-circuit in response to a second scan signal being active during a compensation phase,
the driving sub-circuit is configured to generate a driving current during a light emission phase, the driving current having a magnitude related to the data voltage,
the light emission control sub-circuit is configured to direct the driving current to the light emission sub-circuit in response to a first light emission control signal and a second light emission control signal being active during the light emission phase, and
the light emission sub-circuit is configured to emit light in response to the driving current flowing therethrough during the light emission phase.

### Claim 6 (depends on 5)

The pixel driving circuit of claim 5, wherein the light emission sub-circuit comprises an organic light emitting diode comprising an anode configured to receive the driving current and a cathode configured to receive a ground voltage.

### Claim 7 (depends on 6)

The pixel driving circuit of claim 6, wherein the driving sub-circuit comprises a driving transistor comprising a control electrode, a first electrode and a second electrode.

### Claim 8 (depends on 7)

The pixel driving circuit of claim 7, wherein the compensation sub-circuit comprises:
a third transistor comprising a control electrode configured to receive the second scan signal, a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to the control electrode of the driving transistor;
a fourth transistor comprising a control electrode configured to receive the second scan signal, a first electrode connected to the first node, and a second electrode connected to the first electrode of the driving transistor; and
a first capacitor connected between the power supply terminal and the control electrode of the driving transistor.

### Claim 9 (depends on 8)

The pixel driving circuit of claim 8, wherein the light emission control sub-circuit comprises:
a fifth transistor comprising a control electrode configured to receive the second light emission control signal, a first electrode connected to the power supply terminal, and a second electrode connected to the first electrode of the driving transistor; and
a sixth transistor comprising a control electrode configured to receive the first light emission control signal, a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to the anode of the organic light emitting diode.

### Claim 10 (depends on 9)

The pixel driving circuit of claim 9, wherein the reset sub-circuit comprises:
a seventh transistor comprising a control electrode configured to receive the first scan signal, a first electrode connected to the control electrode of the driving transistor, and a second electrode configured to receive the reset voltage; and
an eighth transistor comprising a control electrode configured to receive the first scan signal, a first electrode configured to receive the reset voltage, and a second electrode connected to the anode of the organic light emitting diode.

### Claim 11 (depends on 1)

A display device comprising a plurality of the pixel driving circuits as recited in claim 1.

### Claim 12 (depends on 11)

The display device of claim 11, wherein the multiplexing control circuits of the N multiplexing circuits are configured such that the data line is sequentially coupled to the first nodes of the N pixel circuits.

### Claim 13 (depends on 11)

The display device of claim 11, wherein the multiplexing control circuit of the i-th one of the N multiplexing circuits comprises a first transistor comprising:
a control electrode configured to receive the i-th multiplexing control signal;
a first electrode connected to the data line; and
a second electrode connected to the first node of the i-th one of the N pixel circuits.

### Claim 14 (depends on 11)

The display device of claim 11, wherein the reset circuit of the (j+1)-th one of the N multiplexing circuits comprises a second transistor comprising:
a control electrode configured to receive the j-th multiplexing control signal;
a first electrode connected to the first node of the (j+1)-th one of the N pixel circuits; and
a second electrode connected to the power supply terminal of the (j+1)-th one of the N pixel circuits.

### Claim 15 (depends on 11)

The display device of claim 11, wherein each of the N pixel circuits comprises a compensation sub-circuit, a driving sub-circuit, a light emission control sub-circuit, a reset sub-circuit, and a light emission sub-circuit, wherein
the reset sub-circuit is configured to reset the driving sub-circuit and the light emission sub-circuit with a reset voltage in response to a first scan signal being active during a reset phase,
the compensation sub-circuit is configured to transfer the data voltage at the first node to the driving sub-circuit in response to a second scan signal being active during a compensation phase,
the driving sub-circuit is configured to generate a driving current during a light emission phase, the driving current having a magnitude related to the data voltage,
the light emission control sub-circuit is configured to direct the driving current to the light emission sub-circuit in response to a first light emission control signal and a second light emission control signal being active during the light emission phase, and
the light emission sub-circuit is configured to emit light in response to the driving current flowing therethrough during the light emission phase.

### Claim 16 (depends on 15)

The display device of claim 15, wherein the light emission sub-circuit comprises an organic light emitting diode comprising an anode configured to receive the driving current and a cathode configured to receive a ground voltage.

### Claim 17

A method of driving a pixel driving circuit, wherein the pixel driving circuit comprises: N pixel circuits, each of the pixel circuits comprising a first node and a power supply terminal, the first node configured to receive a data voltage, the power supply terminal configured to receive a power supply voltage, wherein N is an integer greater than 1; and N multiplexing circuits configured to selectively couple a data line to the first nodes of the N pixel circuits, wherein a first one of the N multiplexing circuits comprises a multiplexing control circuit, and a second one to an N-th one of the N multiplexing circuits comprise respective multiplexing control circuits and respective reset circuits, wherein the multiplexing control circuit of an i-th one of the N multiplexing circuits is configured to couple the data line to the first node of an i-th one of the N pixel circuits in response to an i-th multiplexing control signal being active, i being an integer and 1≤i≤N, and the reset circuit of a (j+1)-th one of the N multiplexing circuits is configured to reset the first node of a (j+1)-th one of the N pixel circuits with the power supply voltage in response to a j-th multiplexing control signal being active, j being an integer and 1≤j<N,
the method comprising:
supplying the j-th multiplexing control signal that is active to the multiplexing control circuit of a j-th one of the N multiplexing circuits such that the data voltage on the data line is transferred to the first node of a j-th one of the N pixel circuits, and that the first node of the (j+1)-th one of the N pixel circuits is reset to the power supply voltage.

### Claim 18 (depends on 17)

The method of claim 17, wherein each of the N pixel circuits comprises a compensation sub-circuit, a driving sub-circuit, a light emission control sub-circuit, a reset sub-circuit, and a light emission sub-circuit, the method further comprising:
performing a reset phase in which the reset sub-circuit resets the driving sub-circuit and the light emission sub-circuit with a reset voltage;
performing a compensation phase in which the compensation sub-circuit transfers the data voltage at the first node to the driving sub-circuit; and
performing a light emission phase in which the driving sub-circuit generates a driving current having a magnitude related to the data voltage, the light emission control sub-circuit directs the driving current to the light emission sub-circuit, and the light emission sub-circuit emits light in response to the driving current flowing therethrough,
wherein the supplying of the j-th multiplexing control signal that is active to the multiplexing control circuit of the j-th one of the N multiplex circuits is performed in the compensation phase.

### Claim 19 (depends on 18)

The method of claim 18, wherein the performing the compensation phase further comprises:
sequentially coupling, by the multiplexing control circuits of the N multiplexing circuits, the data line to the first nodes of the N pixel circuits such that respective data voltages are sequentially transferred to the driving sub-circuits of the N pixel circuits.

### Claim 20 (depends on 19)

The method of claim 19, wherein
in the reset phase, the reset sub-circuits of the N pixel circuits simultaneously reset the driving sub-circuits and the light emission sub-circuits of the N pixel circuits; and
in the light emission phase, the light emission control sub-circuits of the N pixel circuits simultaneously direct respective driving currents to the light emission sub-circuits of the N pixel circuits such that the light emission sub-circuits simultaneously emit light.