# US 11,308,872 B2 · OLED display panel for minimizing area of internalconnection line part for connecting GIP dirving circuit located in active area and OLED display device comprising the same

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- Number: US 11,308,872 B2
- Document ID: US11308872B2
- Status: Granted
- Kind: B2
- Application number: 16/174,721
- Filed: 2018-10-30
- Published: 2019-05-30
- Granted: 2022-04-19
- Earliest claimed: 2017-11-27
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Kyung-Min Kim; In-Hyo Han; Hun-Ki Shin
- Web page: https://patentgrep.com/patent/US11308872B2

## CPC

- G09G 3/3225: using an active matrix
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/3266: Details of drivers for scan electrodes
- H03K 3/027: by the use of logic circuits, with internal or external positive feedback
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10K 59/179: Interconnections, e.g. wiring lines or terminals
- H10K 59/351: {comprising more than three subpixels, e.g. red-green-blue-white [RGBW]}
- G09G 2230/00: Details of flat display driving waveforms
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

The present disclosure relates to an OLED display panel for minimizing the size of a bezel and includes: an active area including data lines, scan lines intersecting the data lines, and sub-pixels arranged at each intersection; and a stage of a GIP driving circuit distributed and arranged in a plurality of unit pixel regions driven by m (m being a natural number) scan lines in the active area, to supply scan pulses to the corresponding scan lines, wherein the active area further includes m GIP internal connection lines parts respectively adjacent to the m scan lines, and a plurality of internal connection lines for connecting elements constituting each stage is distributed and arranged in the m GIP internal connection line parts.

## Claims

### Claim 1

An OLED display panel, comprising:
a plurality of data lines and a plurality of scan lines intersecting the plurality of data lines, and a plurality of sub-pixels arranged at each intersection of the plurality of data lines and the plurality of scan lines at an active area;
a stage of a gate in panel (GIP) driving circuit including m (m being a natural number of 2 or more) scan pulse output units outputting m scan pulses to m scan lines, wherein a plurality of elements constituting the stage of the GIP driving circuit are arranged in a plurality of unit pixel regions of m horizontal lines driven by the m scan lines in the active area;
m GIP internal connection line parts respectively adjacent to the m scan lines at the active area; and
a plurality of internal connection lines connecting the plurality of elements constituting the stage of the GIP driving circuit and the m GIP internal connection line parts,
wherein each scan line and each GIP internal connection line part are parallel with each other, and
wherein the number of the m GIP internal connection line parts corresponds to the number of the m scan lines.

### Claim 2 (depends on 1)

The OLED display panel according to claim 1, wherein the stage further includes:
a logic unit controlling voltage levels of a first node and a second node using a carry pulse of a previous stage and a carry pulse of a next stage; and
a carry pulse output unit outputting an input carry pulse output clock signal as a carry pulse in response to the voltage levels of the first node and the second node.

### Claim 3 (depends on 1)

The OLED display panel according to claim 1, wherein at least one of the unit pixel regions includes at least three sub-pixels, a GIP part in which one of the plurality of elements constituting the stage of the GIP driving circuit is arranged, and at least one of the plurality of internal connection lines electrically connected to the one of the plurality of elements and the m GIP internal connection line parts.

### Claim 4 (depends on 1)

The OLED display panel according to claim 1, wherein m GIP internal connection line parts include a node Q, a node Qb, a node Qh, a carry pulse output terminal of the previous stage and a carry pulse output terminal of the next stage, in areas respectively adjacent to the m scan lines.

### Claim 5 (depends on 1)

The OLED display panel according to claim 1, wherein the m includes one of 2, 3 and 5.

### Claim 6 (depends on 1)

The OLED display panel according to claim 1, wherein one of the plurality of elements constituting the stage is located between two adjacent unit pixels and is connected to at least one of the m GIP internal connection line parts through at least one of the plurality of internal connection lines.

### Claim 7 (depends on 1)

The OLED display panel according to claim 1, wherein the plurality of internal connection lines are located in a direction perpendicular to the m GIP internal connection line parts between two adjacent unit pixels.