# US 11,308,860 B2 · Pixel circuit and driving method, pixel unit, display panel

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- Number: US 11,308,860 B2
- Document ID: US11308860B2
- Status: Granted
- Kind: B2
- Application number: 16/605,932
- Filed: 2019-05-10
- Published: 2021-10-28
- Granted: 2022-04-19
- Earliest claimed: 2018-07-04
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: BOE Technology Group Co., Ltd.
- Inventors: Ning Cong; Minghua Xuan; Han Yue; Ming Yang; Xiaochuan Chen; Detao Zhao; Liang Chen; Can Zhang; Can Wang
- Web page: https://patentgrep.com/patent/US11308860B2

## CPC

- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 2300/0857: Static memory circuit, e.g. flip-flop
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present application discloses a pixel circuit and its driving method. The pixel circuit includes an input circuit, a control circuit, and 2N output circuits with N being a positive integer. The input circuit is configured to control a voltage level of a respective one of N control nodes under control of a gate-driving signal from each gate line and a first control signal. The control circuit is configured to respectively control a voltage level of each of 2N switching nodes under control of the N control nodes. The 2N output circuits are respectively connected to 2N data-signal terminals and the 2N switching nodes. Among the 2N output circuits, an i-th output circuit is configured to input an i-th data signal from an i-th data-signal terminal of the 2N data-signal terminals to an emission circuit under control of an i-th switching node of the 2N switching nodes.

## Claims

### Claim 1

A pixel circuit comprising:
an input circuit respectively connected with N gate lines, a control line, and N control nodes, the input circuit being configured to control voltage levels of the N control nodes under control of a respective one gate-driving signal from a respective one of the N gate lines and under control of a first control signal from the control line;
a control circuit respectively connected with the N control nodes and 2N switching nodes, the control circuit being configured to control a voltage level of a respective one of the 2N switching nodes under control of the N control nodes; and
2N output circuits respectively connected with 2N data-signal terminals, the 2N output circuits being connected with the 2N switching nodes, wherein an i-th output circuit of the 2N output circuits is coupled respectively with an i-th switching node of the 2N switching nodes, an i-th data-signal terminal of the 2N data-signal terminals, and an emission circuit, the i-th output circuit being configured to output an i-th data signal from the i-th data-signal terminal under control of the i-th switching node, wherein N is a positive integer, i is a positive integer no greater than N;
wherein the N is 2; the control circuit includes a latch subcircuit, a first control subcircuit, and a second control subcircuit; the 2N switching nodes include a first switching node, a second switching node, a third switching node, and a fourth switching node; the N control nodes include a first control node and a second control node;
the latch subcircuit being connected respectively to the first control node and a latch node configured to set a voltage level thereof under control of the first control node;
the first control subcircuit being connected respectively to the latch node, the second control node, the first switching node, and a second switching node, the first control subcircuit being configured to respectively set voltage levels of the first switching node and the second switching node under control of the latch node and the second control node;
the second control subcircuit being connected respectively to the first control node, the second control node, the third switching node, and the fourth switching node, the second control subcircuit being configured to respectively set voltage levels of the third switching node and the fourth switching node under control of the first control node and the second control node.

### Claim 2 (depends on 1)

The pixel circuit of claim 1, wherein the first control subcircuit comprises a first control unit-circuit and a second control unit-circuit; the second control subcircuit comprises a third control unit-circuit and a fourth control unit-circuit;
the first control unit-circuit being connected respectively to the latch node, the second control node, the first switching node, and the second switching node, and being configured to respectively set voltage levels of the first switching node and the second switching node under control of the latch node and the second control node;
the second control unit-circuit being connected respectively to the latch node, a pull-down power supply, the first switching node, and the second switching node, and being configured to respectively set voltage levels of the first switching node and the second switching node under control of a pull-down voltage from the pull-down power supply;
the third control unit-circuit being connected respectively to the first control node, the second control node, the third switching node, and the fourth switching node, and being configured to respectively set voltage levels of the third switching node and the fourth switching node under control of the first control node and the second control node;
the fourth control unit-circuit being connected respectively to the first control node, the pull-down power supply, the third switching node, and the fourth switching node, and being configured to respectively set voltage levels of the third switching node and the fourth switching node under control of the first control node and the pull-down voltage.

### Claim 3 (depends on 2)

The pixel circuit of claim 2, wherein the first control unit-circuit comprises a first latch having an input terminal connected to the second control node and an output terminal connected to the first switching node;
the third control unit-circuit comprises a second latch having an input terminal connected to the second control node and an output terminal connected to the third control node.

### Claim 4 (depends on 3)

The pixel circuit of claim 3, wherein the first latch comprises a first tri-state gate and a second tri-stage gate, the second latch comprises a third tri-state gate and a fourth tri-state gate;
the first tri-state gate comprising a control terminal connected to the latch node, an input terminal connected to the second control node, and an output terminal connected to the first switching node;
the second tri-state gate comprising a control terminal connected to the latch node, an input terminal connected to the first switching node, and an output terminal connected to the second control node;
the third tri-state gate comprising a control terminal connected to the first control node, an input terminal connected to the second control node, and an output terminal connected to the third switching node; and
the fourth tri-state gate comprising a control terminal connected to the first control node, an input terminal connected to the third switching node, and an output terminal connected to the second control node.

### Claim 5 (depends on 2)

The pixel circuit of claim 2, wherein the second control unit-circuit comprises a first transistor and a second transistor; the fourth control unit-circuit comprises a third transistor and a fourth transistor;
the first transistor having a gate terminal connected to the latch node, a first terminal connected to the pull-down power supply, and a second terminal connected to the first switching node;
the second transistor having a gate terminal connected to the latch node, a first terminal connected to the pull-down power supply, and a second terminal connected to the second switching node;
the third transistor having a gate terminal connected to the first control node, a first terminal connected to the pull-down power supply, and a second terminal connected to the third switching node; and
the fourth transistor having a gate terminal connected to the first control node, a first terminal connected to the pull-down power supply, and a second terminal connected to the fourth switching node.

### Claim 6 (depends on 1)

The pixel circuit of claim 1, wherein the latch subcircuit comprises a third latch having an input terminal connected to the first control node and an output terminal connected to the latch node.

### Claim 7 (depends on 6)

The pixel circuit of claim 6, wherein the third latch comprises a first non-gate and a second non-gate;
the first non-gate having an input terminal connected to the first control node and an output terminal connected to the latch node; and
the second non-gate having an input terminal connected to the latch node and an output terminal connected to the first control node.

### Claim 8 (depends on 1)

The pixel circuit of claim 1, wherein the N is 1, the 2N switching nodes includes a first switching node and a third switching node, the N control node is a first control node; the control circuit being connected respectively to the first control node, the first switching node, and the third switching node, and being configured to set voltage levels of the first switching node and the third switching node under control of the first control node.

### Claim 9 (depends on 1)

The pixel circuit of claim 1, wherein the i-th output circuit comprises an i-th output transistor having a gate terminal connected to the i-th switching node, a first terminal connected to the i-th data-signal terminal, and a second terminal connected to the emission circuit.

### Claim 10 (depends on 1)

The pixel circuit of claim 1, wherein the input circuit comprises N input transistors among which a j-th input transistor having a gate terminal connected to a j-th gate line, a first terminal connected to the control line, and a second terminal connected to a j-th control node, wherein j is a positive integer no greater than N.

### Claim 11 (depends on 1)

A driving method of a pixel circuit of claim 1, comprising:
providing a gate-driving signal at a turn-on voltage level to a j-th gate line of the N gate lines so that the input circuit transports a first control signal in the control line to a corresponding j-th control node of the N control nodes, wherein j is a positive integer no greater than N;
setting one switching node of the 2N switching nodes to a turn-on voltage level under control of the N control nodes so that a corresponding one output circuit connected to the one switching node is to input a data signal from a corresponding data-signal terminal connected to the corresponding one output circuit to the emission circuit, wherein the 2N output circuits are connected respectively to the 2N switching nodes, the 2N output circuits are connected respectively to 2N data-signal terminals, the 2N data-signal terminals supply different data signals.

### Claim 12 (depends on 11)

The method of claim 11, wherein the 2N data-signal terminals supply different data signals with different amplitudes.

### Claim 13 (depends on 11)

The method of claim 11, wherein the 2N data-signal terminals supply different data signals with different duty cycles.

### Claim 14 (depends on 11)

The method of claim 11, wherein the N is 2, the control circuit includes a latch subcircuit, a first control subcircuit, and a second control subcircuit; the 2N switching nodes includes a first switching node, a second switching node, a third switching node, and a fourth switching node; the N control nodes includes a first control node and a second control node; the method comprising:
setting the first control node at a turn-off voltage level and the second control node at a turn-off voltage level, so that the control circuit sets the first switching node to the turn-off voltage level, the second switching node to the turn-off voltage level, the third switching node to a turn-on voltage level, and the fourth switching node to the turn-off voltage level;
setting the first control node at a turn-off voltage level and the second control node at a turn-on voltage level, so that the control circuit sets the first switching node to the turn-off voltage level, the second switching node to the turn-off voltage level, the third switching node to the turn-off voltage level, and the fourth switching node to the turn-on voltage level;
setting the first control node at a turn-on voltage level and the second control node at a turn-off voltage level, so that the control circuit sets the first switching node to the turn-on voltage level, the second switching node to the turn-off voltage level, the third switching node to the turn-off voltage level, and the fourth switching node to the turn-off voltage level; and
setting the first control node at a turn-on voltage level and the second control node at the turn-on voltage level, so that the control circuit sets the first switching node to a turn-off voltage level, the second switching node to the turn-on voltage level, the third switching node to the turn-off voltage level, and the fourth switching node to the turn-off voltage level.

### Claim 15 (depends on 11)

The method of claim 11, wherein the N is 1, the 2N switching nodes includes a first switching node and a third switching node, the N control node is a first control node; the method comprising:
setting the first control node to a turn-on voltage level, so that the control circuit sets the first switching node to a turn-off voltage level and the third switching node to the turn-on voltage level; and
setting the first control node to a turn-off voltage level, so that the control circuit sets the first switching node to a turn-on voltage level and the third switching node to the turn-off voltage level.

### Claim 16 (depends on 1)

A pixel unit comprising an emission circuit and a pixel circuit of claim 1, wherein the pixel circuit comprises an output circuit coupled to the emission circuit.

### Claim 17 (depends on 16)

The pixel unit of claim 16, wherein the emission circuit comprises a switching subcircuit and an emitting subcircuit; the switching subcircuit being connected respectively to a second control-signal terminal, the output circuit being connected to the emitting subcircuit, the switching subcircuit being configured to input a signal from the output circuit to the emitting subcircuit under control of a second control signal from the second control-signal terminal.

### Claim 18 (depends on 16)

The pixel unit of claim 16, wherein the emission circuit comprises a switching subcircuit and an emitting subcircuit; the switching subcircuit being connected respectively to a second control-signal terminal, a pull-up power supply, the output circuit, and the emitting subcircuit, the switching subcircuit being configured to input a pull-up voltage signal from the pull-up power supply to the emitting subcircuit under control of a second control signal from the second control-signal terminal.

### Claim 19 (depends on 16)

A display panel comprising a plurality of pixel units, each of the plurality of pixel units being the pixel unit of claim 16.