# US 11,308,857 B2 · Gate driver and display device including the same

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- Number: US 11,308,857 B2
- Document ID: US11308857B2
- Status: Granted
- Kind: B2
- Application number: 17/202,960
- Filed: 2021-03-16
- Published: 2022-01-27
- Granted: 2022-04-19
- Earliest claimed: 2020-07-24
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Hai Jung In
- Web page: https://patentgrep.com/patent/US11308857B2

## CPC

- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3674: {Details of drivers for scan electrodes}
- G09G 2310/0278: Details of driving circuits arranged to drive both scan and data electrodes
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2330/028: Generation of voltages supplied to electrode drivers in a matrix display other than LCD
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A gate driver includes first and second stages. Each of the first and second stages includes an output circuit which outputs a scan signal, a carry signal and an inverted carry signal based on voltages of first and second nodes, a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The first stage further includes a first input circuit which controls the voltages of the first and second nodes thereof based on a start pulse and a signal supplied to the second input terminal. The second stage further includes a second input circuit which controls the voltages of the first and second nodes thereof based on a first carry signal and a first inverted carry signal, and a signal supplied to the second input terminal. The second stage is dependently connected to the first stage.

## Claims

### Claim 1

A gate driver comprising:
a first stage and a second stage,
wherein each of the first stage and the second stage comprises an output circuit which outputs a scan signal, a carry signal and an inverted carry signal based on a voltage of a first node and a voltage of a second node, a first input terminal, a second input terminal, a third input terminal, a first output terminal from which the scan signal and the carry signal are output, and a second output terminal from which the inverted carry signal is output, wherein the second input terminal of the first stage and the third input terminal of the second stage receive a first clock signal, and the third input terminal of the first stage and the second input terminal of the second stage receive a second clock signal,
wherein the first stage further comprises:
a first input circuit which controls the voltage of the first node thereof and the voltage of the second node thereof based on a start pulse and a signal supplied to the second input terminal of the first stage,
wherein the second stage further comprises:
a second input circuit which controls the voltage of the first node thereof and the voltage of the second node thereof based on a first carry signal and a first inverted carry signal supplied from the output circuit of the first stage, and a signal supplied to the second input terminal of the second stage, and
wherein the second stage is dependently connected to the first stage.

### Claim 2 (depends on 1)

The gate driver according to claim 1, wherein the first input circuit comprises:
a first input transistor connected between the first input terminal of the first stage, to which the start pulse is supplied, and the first node of the first stage, and including a gate electrode connected to the second input terminal of the first stage;
a second input transistor connected between the second input terminal of the first stage and the second node of the first stage, and including a gate electrode connected to the first node of the first stage; and
a third input transistor connected between a first power and the second node of the first stage, and including a gate electrode connected to the second input terminal of the first stage.

### Claim 3 (depends on 2)

The gate driver according to claim 2, wherein the second input circuit comprises:
a first transistor connected between the first input terminal of the second stage, to which the first carry signal is supplied, and the first node of the second stage, and including a gate electrode connected to the second input terminal of the second stage; and
a second transistor connected between an additional input terminal of the second stage to which the first inverted carry signal is supplied and the second node of the second stage, and including a gate electrode connected to the second input terminal of the second stage.

### Claim 4 (depends on 1)

The gate driver according to claim 1, wherein each of the first stage and the second stage further comprises:
a control circuit which controls a low level voltage of a third node based on a signal supplied to the third input terminal; and
a stabilizing circuit electrically connected between the first or second input circuit and the output circuit including the third node and a fourth node, wherein the stabilizing circuit limits a voltage drop amount of the first node and a voltage drop amount of the second node.

### Claim 5 (depends on 4)

The gate driver according to claim 4, wherein each output circuit comprises:
a fourth transistor connected between a first power and the first output terminal, and including a gate electrode connected to the third node;
a fifth transistor connected between a second power and the first output terminal, and including a gate electrode connected to the fourth node;
a sixth transistor connected between the fourth node and a fifth node, and including a gate electrode connected to the third input terminal;
a seventh transistor connected to the fifth node and the third input terminal, and including a gate electrode connected to a sixth node;
an eighth transistor connected between the second power and the fourth node, and including a gate electrode connected to the first node;
a first capacitor connected between the fifth node and the sixth node; and
a second capacitor connected between the second power and the fourth node.

### Claim 6 (depends on 5)

The gate driver according to claim 5, wherein the second output terminal is connected to the fifth node.

### Claim 7 (depends on 5)

The gate driver according to claim 5, wherein the second output terminal is connected to the fourth node.

### Claim 8 (depends on 5)

The gate driver according to claim 5, wherein the stabilizing circuit comprises:
a tenth transistor connected between the first node and the third node, and including a gate electrode which receives a voltage of the first power; and
an eleventh transistor connected between the second node and the sixth node, and including a gate electrode which receives the voltage of the first power.

### Claim 9 (depends on 4)

The gate driver according to claim 4, wherein the control circuit comprises:
a ninth transistor including a first electrode connected to the third input terminal, and a gate electrode connected to the third node; and
a third capacitor connected between a second electrode of the ninth transistor and the gate electrode of the ninth transistor.

### Claim 10 (depends on 4)

The gate driver according to claim 4, wherein each of the first stage and the second stage further comprises:
an initialization circuit which supplies a voltage of a second power to the first node during an initialization period.

### Claim 11 (depends on 10)

The gate driver according to claim 10, wherein the initialization circuit comprises:
a twelfth transistor connected between the second power and the first node, and including a gate electrode which receives a reset signal.

### Claim 12 (depends on 11)

The gate driver according to claim 11, wherein the initialization circuit of the second stage further comprises:
a thirteenth transistor connected between the fourth node and a fourth input terminal, to which the reset signal is supplied, and including a gate electrode connected to the fourth input terminal or a first power.

### Claim 13 (depends on 10)

The gate driver according to claim 10, wherein the initialization circuit of the first stage further comprises:
a twelfth transistor connected between the second power and the first node, and including a gate electrode which receives a reset signal.

### Claim 14 (depends on 13)

The gate driver according to claim 13, wherein the initialization circuit of the first stage further comprises:
a thirteenth transistor connected between the twelfth transistor and the second power, and including a gate electrode connected to the third input terminal.

### Claim 15 (depends on 10)

The gate driver according to claim 10, wherein the initialization circuit of the second stage comprises:
a twelfth transistor and a thirteenth transistor connected in series between the second power and the first node; and
a fourteenth transistor and a fifteenth transistor connected in series between a first power and the fourth node,
wherein a gate electrode of the twelfth transistor is connected to one of the second input terminal and the third input terminal, and a gate electrode of the thirteenth transistor is connected to the other of the second input terminal and the third input terminal, and
wherein a gate electrode of the fourteenth transistor is connected to one of ones of the second input terminal and the third input terminal, and a gate electrode of the fifteenth transistor is connected to the other of the second input terminal and the third input terminal.

### Claim 16 (depends on 10)

The gate driver according to claim 10, wherein
the first stage and the second stage simultaneously output the scan signal having a high level during the initialization period.

### Claim 17 (depends on 9)

The gate driver according to claim 9, wherein the control circuit further comprises:
a sixteenth transistor connected between second power and the second electrode of the ninth transistor, and including a gate electrode connected to the second node.

### Claim 18 (depends on 9)

The gate driver according to claim 9, wherein the control circuit further comprises:
a sixteenth transistor and a seventeenth transistor connected in series between the first input terminal and the gate electrode of the ninth transistor; and
an eighteenth transistor connected between the gate electrode of the ninth transistor and the third node, and including a gate electrode connected to the gate electrode of the ninth transistor.

### Claim 19 (depends on 18)

The gate driver according to claim 18, wherein the control circuit further comprises:
a nineteenth transistor connected between second power and the second electrode of the ninth transistor, and including a gate electrode connected to the second node.

### Claim 20

A display device comprising:
pixels;
a gate driver comprising a first stage and a second stage; and
a data driver which supplies data signals to the pixels through data lines,
wherein each of the first stage and the second stage comprises an output circuit which outputs a scan signal, a carry signal and an inverted carry signal based on a voltage of a first node and a voltage of a second node, a first input terminal, a second input terminal, a third input terminal, a first output terminal, from which the scan signal and the carry signal are output, and a second output terminal, from which the inverted carry signal is output, wherein the second input terminal of the first stage and the third input terminal of the second stage receive a first clock signal, and the third input terminal of the first stage and the second input terminal of the second stage receive a second clock signal,
wherein the first stage further comprises:
a first input circuit which controls the voltage of the first node thereof and the voltage of the second node thereof based on a start pulse and a signal supplied to the second input terminal of the first stage,
wherein the second stage further comprises:
a second input circuit which control the voltage of the first node thereof and the voltage of the second node thereof based on a first carry signal and a first inverted carry signal supplied from the output circuit of the first stage, and a signal supplied to the second input terminal of the second stage, and
wherein the second stage is dependently connected to the first stage.