# US 11,308,853 B2 · Shift register and driving method thereof, gate driving circuit and display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,308,853 B2 - Document ID: US11308853B2 - Status: Granted - Kind: B2 - Application number: 16/304,952 - Filed: 2018-02-08 - Published: 2021-07-22 - Granted: 2022-04-19 - Earliest claimed: 2017-07-31 - Assignees: Beijing Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Beijing Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Inventors: Wang Guo; Yanchen Li; Yue Li; Jinyu Li; Dawei Feng; Yu Zhao; Shaojun Hou; Dong Wang; Mingyang Lv - Web page: https://patentgrep.com/patent/US11308853B2 ## CPC - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/3677: {suitable for active matrices only} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0283: Arrangement of drivers for different directions of scanning - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/061: for resetting or blanking - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract There are provided in the present disclosure a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register of the present disclosure includes: a forward scanning input sub-circuit for pre-charging a potential of a pull-up node by an operation level signal under control of a forward input signal and a forward scanning signal upon scanning forwards; a backward scanning input sub-circuit for pre-charging the potential of the pull-up node by an operation level signal under control of a backward input signal and a backward scanning signal upon scanning backwards; an output sub-circuit for outputting a clock signal through a signal output terminal under control of the potential of the pull-up node; wherein the pull-up node is a connection node of the forward scanning input sub-circuit, the backward scanning input sub-circuit and the output sub-circuit. ## Claims ### Claim 1 A shift register, comprising: a forward scanning input sub-circuit for pre-charging a potential of a pull-up node by an operation level signal under control of a forward input signal and a forward scanning signal during forward scanning; a backward scanning input sub-circuit for pre-charging the potential of the pull-up node by an operation level signal under control of a backward input signal and a backward scanning signal during backwards scanning; an output sub-circuit for outputting a clock signal through a signal output terminal under control of the potential of the pull-up node; wherein the pull-up node is a connection node of the forward scanning input sub-circuit, the backward scanning input sub-circuit and the output sub-circuit, said shift register further comprising: a forward scanning reset sub-circuit for resetting the pull-up node by a non-operation level signal under control of a forward reset signal and the forward scanning signal during forwards scanning, said forward scanning input sub-circuit and said forward scanning reset sub-circuit operate independently each other. ### Claim 2 (depends on 1) The shift register according to claim 1, further comprising: a backward scanning reset sub-circuit for resetting the pull-up node by the non-operation level signal under control of a backward reset signal and the backward scanning signal during backwards scanning. ### Claim 3 (depends on 1) The shift register according to claim 1, further comprising: a pull-down control sub-circuit for controlling a potential of a pull-down node under control of the operation level and the potential of the pull-up node; a pull-down sub-circuit for pulling down the potential of the pull-down node by the non-operation level signal under control of the potential of the pull-up node; a noise reduction sub-circuit for reducing an output noise of the pull-up node and the signal output terminal by the non-operation level signal under control of the pull-down node; wherein the pull-down node is a connection node of the pull-down control sub-circuit, the pull-down sub-circuit and the noise reduction sub-circuit. ### Claim 4 (depends on 1) The shift register according to claim 1, wherein the forward scanning input sub-circuit comprises: a first forward scanning input transistor and a second forward scanning input transistor; wherein a control electrode of the second forward scanning input transistor is connected to a forward scanning input terminal, a first electrode of the second forward scanning input transistor is connected to a second electrode of the first forward scanning input transistor, and a second electrode of the second forward scanning input transistor is connected to the pull-up node; a control electrode of the first forward scanning input transistor is connected to a first electrode thereof and is connected to a forward scanning control terminal. ### Claim 5 (depends on 1) The shift register according to claim 1, wherein the backward scanning input sub-circuit comprises: a first backward scanning input transistor and a second backward scanning input transistor; wherein a control electrode of the first backward scanning input transistor is connected to a first electrode thereof, and is connected to a backward scanning control terminal; a control electrode of the second backward scanning input transistor is connected to a backward scanning input terminal, a first electrode of the second backward scanning input transistor is connected to a second electrode of the first backward scanning input transistor, and a second electrode of the second backward scanning input transistor is connected to the pull-up node. ### Claim 6 (depends on 2) The shift register according to claim 2, wherein the forward scanning reset sub-circuit comprises: a first forward scanning reset transistor and a second forward scanning reset transistor; wherein a first electrode of the first forward scanning reset transistor is connected is to the pull-up node, a second electrode of the first forward scanning reset transistor is connected to a first electrode of the second forward scanning reset transistor, and a control electrode of the first forward scanning reset transistor is connected to the backward scanning input terminal; a first electrode of the second forward scanning reset transistor is connected to the second electrode of the first forward scanning reset transistor, a second electrode of the second forward scanning reset transistor is connected to the backward scanning control terminal, and a control electrode of the second forward scanning reset transistor is connected to the forward scanning control terminal. ### Claim 7 (depends on 2) The shift register according to claim 2, wherein the backward scanning reset sub-circuit comprises: a first backward scanning reset transistor and a second backward scanning reset transistor; wherein a first electrode of the first backward scanning reset transistor is connected to a second electrode of the second backward scanning reset transistor, a second electrode of the first backward scanning reset transistor is connected to the pull-up node, and a control electrode of the first backward scanning reset transistor is connected to the forward scanning input terminal; a first electrode of the second backward scanning reset transistor is connected to the forward scanning control terminal, a second electrode of the second backward scanning reset transistor is connected to the first electrode of the first backward scanning reset transistor, and a control electrode of the second backward scanning reset transistor is connected the backward scanning control terminal. ### Claim 8 (depends on 1) The shift register according to claim 1, wherein the output sub-circuit comprises an output transistor and an output capacitor; wherein a control electrode of the output transistor is connected to the pull-up node, a first terminal of the output transistor is connected to a first clock signal terminal, and a second terminal of the output transistor is connected to an output terminal; a first terminal of the output capacitor is connected to the pull-up node, and a second terminal of the output capacitor is connected to the output terminal. ### Claim 9 (depends on 3) The shift register according to claim 3, wherein the pull-down control sub-circuit comprises a first pull-down control transistor and a second pull-down control transistor; wherein a first electrode of the first pull-down control transistor is connected to a first electrode of the second pull-down control transistor, a second electrode of the first pull-down control transistor is connected to the pull-down node, and a control electrode of the first pull-down control transistor is connected to a second electrode of the second pull-down control transistor; both the first electrode and a control electrode of the second pull-down control transistor are connected to a first control signal terminal, and the second electrode of the second pull-down control transistor is connected to the control electrode of the first pull-down control transistor and the pull-down sub-circuit. ### Claim 10 (depends on 3) The shift register according to claim 3, wherein the pull-down sub-circuit comprises: a first pull-down transistor and a second pull-down transistor; wherein a first electrode of the first pull-down transistor is connected to the pull-down node, a second electrode of the first pull-down transistor is connected to a low level terminal, and a control electrode of the first pull-down transistor f is connected to the pull-up node; a first electrode of the second pull-down transistor is connected to the pull-down control sub-circuit, a second electrode of the second pull-down transistor is connected to the low level terminal, and a control electrode of the second pull-down transistor is connected to the pull-up node. ### Claim 11 (depends on 3) The shift register according to claim 3, wherein the noise reduction sub-circuit comprises: a first noise reduction transistor and a second noise reduction transistor; wherein a first electrode of the first noise reduction transistor is connected to the pull-up node, a second electrode of the first noise reduction transistor is connected to a second control signal terminal, and a control electrode of the first noise reduction transistor is connected to the pull-down node; a first electrode of the second noise reduction transistor is connected to the pull-up node, a second electrode of the second noise reduction transistor is connected to the second control signal terminal, and a control electrode of the second noise reduction transistor is connected to the pull-down node. ### Claim 12 (depends on 1) The shift register according to claim 1, further comprising: an output reset sub-circuit for resetting a signal output by the signal output terminal by the non-operation level signal under control of a second control signal after scanning of each frame ends up. ### Claim 13 (depends on 12) The shift register according to claim 12, wherein the output reset sub-circuit comprises: an output reset transistor, wherein a first electrode of the output reset transistor is connected to the signal output terminal, a second electrode of the output reset transistor is connected to a low level signal terminal, and a control electrode of the output reset transistor is connected to the second control signal terminal. ### Claim 14 (depends on 1) A driving method of the shift register according to claim 1, comprising: in a forward scanning pre-charge phase, pre-charging a pull-up node by adopting a forward scanning input sub-circuit; in a backward scanning pre-charge phase, pre-charging the pull-up node by adopting a backward scanning input sub-circuit. ### Claim 15 (depends on 14) The driving method of the shift register according to claim 14, further comprising: in a forward scanning reset phase, resetting the pull-up node by adopting a forward scanning reset sub-circuit; in a backward scanning reset phase, resetting the pull-up node by adopting a backward scanning reset sub-circuit. ### Claim 16 (depends on 14) The driving method of the shift register according to claim 14, wherein the forward scanning pre-charge phase comprises: controlling the forward scanning input sub-circuit to be turned on by a forward input signal provided by a first signal terminal and an operation level signal provided by a forward scanning control terminal, and pre-charging the pull-up node by the operation level signal provided by the forward scanning control terminal; the backward scanning pre-charging phase comprises: controlling the backward scanning input sub-circuit to be turned on by a backward input signal provided by a second signal terminal and an operation level signal provided by the backward scanning control terminal, and pre-charging the pull-up node by the operation level signal provided by the backward scanning control terminal. ### Claim 17 (depends on 15) The driving method of the shift register according to claim 15, wherein the forward scanning reset phase comprises: controlling the forward scanning reset sub-circuit to be turned on by a forward reset signal provided by the second signal terminal and the operation level signal provided by the forward scanning control terminal, and resetting the pull-up node by a non-operation level signal provided by the backward scanning control terminal; the backward scanning reset phase comprises: controlling the backward scanning reset sub-circuit to be turned on by a backward reset signal provided by the first signal terminal and an operation level signal provided by the backward scanning control terminal, and resetting the pull-up node by a non-operation level signal provided by the forward scanning control terminal. ### Claim 18 (depends on 1) A gate driving circuit, comprising multiple shift registers connected in cascades, wherein the shift register is the shift register according to claim 1. ### Claim 19 (depends on 18) A display apparatus, comprising the gate driving circuit according to claim 18.