# US 11,308,843 B2 · Output buffer circuit for display driving apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,308,843 B2 - Document ID: US11308843B2 - Status: Granted - Kind: B2 - Application number: 17/368,599 - Filed: 2021-07-06 - Published: 2022-01-13 - Granted: 2022-04-19 - Earliest claimed: 2020-07-09 - Assignees: Silicon Works Co., Ltd. - Applicants: Silicon Works Co., Ltd. - Inventors: Young Bok Kim; Taiming Piao; Young Tae Kim; Young Ho Shin - Web page: https://patentgrep.com/patent/US11308843B2 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/2011: {by amplitude modulation} - G09G 3/3283: in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements - H03K 3/356017: {using additional transistors in the input circuit (H03K3/356104, H03K3/3562 take precedence)} - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2320/0276: for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction - H03M 1/66: Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) - H03M 1/742: {using current sources as quantisation value generators} - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Disclosed is an output buffer circuit for a display driving apparatus, which generates an output voltage by using a bias current controlled by digital-to-analog conversion for interpolation data, the output buffer circuit including a decoder configured to output control data obtained by decoding interpolation data, and an output circuit configured to output an output voltage by using a bias current having the amount of current controlled by digital-to-analog conversion for the control data. ## Claims ### Claim 1 An output buffer circuit for a display driving apparatus, comprising: a decoder configured to receive interpolation data and output control data obtained by decoding the interpolation data; an input stage configured to receive a high input voltage, a low input voltage, a feedback output voltage and the control data, output a positive current and a first feedback current in accordance with one of a first input group comprising the high input voltage and the feedback output voltage and a second input group comprising the low input voltage and the feedback output voltage, and output a negative current and a second feedback current in accordance with the other of the first input group and the second input group; and an output stage configured to output an output voltage having a level determined by pull-up based on the positive current and the first feedback current and pull-down based on the negative current and the second feedback current, wherein the output voltage corresponds to the feedback output voltage, and the input stage controls a bias current so that the bias current has an amount of current non-linearly varying in response to a change in a value of the control data, and outputs the positive current, the first feedback current, the negative current and the second feedback current by using the bias current. ### Claim 2 (depends on 1) The output buffer circuit of claim 1, wherein the decoder outputs the control data having more bits than the interpolation data, stores mapping information in which values of the interpolation data and values of the control data are mapped, and outputs the control data obtained by decoding the interpolation data by using the mapping information. ### Claim 3 (depends on 2) The output buffer circuit of claim 2, wherein the decoder decodes the interpolation data having three bits into the control data having eight bits by using the mapping information. ### Claim 4 (depends on 1) The output buffer circuit of claim 1, wherein the input stage comprises: a positive circuit configured to control a positive bias current so that the positive bias current has an amount of current corresponding to the control data in order to compensate for an offset, and to output the positive current and the first feedback current corresponding to one of the first input group comprising the high input voltage and the feedback output voltage and the second input group comprising the low input voltage and the feedback output voltage by using the positive bias current; and a negative circuit configured to control a negative bias current so that the negative bias current has the amount of current corresponding to the control data in order to compensate for the offset, and to output the negative current and the second feedback current corresponding to the other of the first input group comprising the high input voltage and the feedback output voltage and the second input group comprising the low input voltage and the feedback output voltage by using the negative bias current. ### Claim 5 (depends on 4) The output buffer circuit of claim 4, wherein the positive circuit comprises: a first current supply circuit configured to provide a first positive bias current having an amount of current corresponding to non-inverted control data and a second positive bias current having an amount of current corresponding to inverted control data; a first bias unit configured to provide the positive current and the first feedback current corresponding to the high input voltage and the feedback output voltage by using the first positive bias current of the first current supply circuit; and a second bias unit configured to provide the positive current and the first feedback current corresponding to the low input voltage and the feedback output voltage by using the second positive bias current of the first current supply circuit. ### Claim 6 (depends on 5) The output buffer circuit of claim 5, wherein the first current supply circuit comprises: a plurality of first current sources connected to a ground voltage and set to have identical or different amounts of current; a first switching circuit comprising a plurality of first switches configured to correspond to bits of the non-inverted control data, respectively, wherein the plurality of first switches is connected to the plurality of first current sources in a one-to-one way and switched in response to values of the bits of the non-inverted control data, respectively, so that the first positive bias current is provided to the first bias unit; and a second switching circuit comprising a plurality of second switches configured to correspond to bits of the inverted control data, respectively, wherein the plurality of second switches is connected to the plurality of first current sources in a one-to-one way and switched in response to values of the bits of the inverted control data, respectively, thereby providing the second positive bias current to the second bias unit. ### Claim 7 (depends on 4) The output buffer circuit of claim 4, wherein the negative circuit comprises: a second current supply circuit configured to provide a first negative bias current having an amount of current corresponding to non-inverted control data and a second negative bias current having an amount of current corresponding to inverted control data; a third bias unit configured to provide the negative current and the second feedback current corresponding to the high input voltage and the feedback output voltage by using the first negative bias current of the second current supply circuit; and a fourth bias unit configured to provide the negative current and the second feedback current corresponding to the low input voltage and the feedback output voltage by using the second negative bias current of the second current supply circuit. ### Claim 8 (depends on 7) The output buffer circuit of claim 7, wherein the second current supply circuit comprises: a plurality of second current sources connected to a power source voltage and set to have identical or different amounts of current; a third switching circuit comprising a plurality of third switches configured to correspond to bits of the non-inverted control data, respectively, wherein the plurality of third switches is connected to the plurality of second current sources in a one-to-one way and switched in response to values of the bits of the non-inverted control data, respectively, so that the first negative bias current is provided to the third bias unit; and a fourth switching circuit comprising a plurality of fourth switches configured to correspond to bits of the inverted control data, respectively, wherein the plurality of fourth switches is connected to the plurality of second current sources in a one-to-one way and switched in response to values of the bits of the inverted control data, respectively, so that the second negative bias current is provided to the fourth bias unit. ### Claim 9 An output buffer circuit for a display driving apparatus, comprising: a decoder configured to receive interpolation data and output control data obtained by decoding the interpolation data; and an output circuit configured to generate a bias current having an amount of current non-linearly varying in response to a change in a value of the control data by digital-to-analog conversion for the control data, generate a positive current, a first feedback current, a negative current and a second feedback current corresponding to a high input voltage, a low input voltage and a feedback output voltage by using the bias current, and output an output voltage having a level determined by pull-up based on the positive current and the first feedback current and pull-down based on the negative current and the second feedback current, wherein the output voltage corresponds to the feedback output voltage. ### Claim 10 (depends on 9) The output buffer circuit of claim 9, wherein: the interpolation data is received to form lower bits of display data and to have values for interpolating a voltage value between the high input voltage and the low input voltage, and the control data has more bits than the interpolation data. ### Claim 11 (depends on 9) The output buffer circuit of claim 9, wherein the decoder outputs the control data having more bits than the interpolation data, stores mapping information in which values of the interpolation data and values of the control data are mapped, and outputs the control data obtained by decoding the interpolation data by using the mapping information. ### Claim 12 (depends on 11) The output buffer circuit of claim 11, wherein the decoder decodes the interpolation data having three bits into the control data having eight bits by using the mapping information. ### Claim 13 (depends on 9) The output buffer circuit of claim 9, wherein the output circuit comprises: a positive circuit configured to control a positive bias current so that the positive bias current has an amount of current corresponding to the control data, and to generate the positive current and the first feedback current corresponding to one of a first input group comprising the high input voltage and the feedback output voltage and a second input group comprising the low input voltage and the feedback output voltage by using the positive bias current; and a negative circuit configured to control a negative bias current so that the negative bias current has the amount of current corresponding to the control data, and to generate the negative current and the second feedback current corresponding to the other of the first input group comprising the high input voltage and the feedback output voltage and the second input group comprising the low input voltage and the feedback output voltage by using the negative bias current. ### Claim 14 (depends on 13) The output buffer circuit of claim 13, wherein the positive circuit comprises: a first current supply circuit comprising a plurality of first current sources connected to a ground voltage and set to have identical or different amounts of current, and configured to provide a first positive bias current having an amount of current based on at least some of the plurality of first current sources selected by non-inverted control data and a second positive bias current having an amount of current based on at least some of the plurality of first current sources selected by inverted control data; a first bias unit configured to provide the positive current and the first feedback current corresponding to the high input voltage and the feedback output voltage by using the first positive bias current of the first current supply circuit; and a second bias unit configured to provide the positive current and the first feedback current corresponding to the low input voltage and the feedback output voltage by using the second positive bias current of the first current supply circuit. ### Claim 15 (depends on 13) The output buffer circuit of claim 13, wherein the negative circuit comprises: a second current supply circuit comprising a plurality of second current sources connected to a power source voltage and set to have identical or different amounts of current, and configured to provide a first negative bias current having an amount of current based on at least some of the plurality of second current sources selected by non-inverted control data and a second negative bias current having an amount of current based on at least some of the plurality of second current sources selected by inverted control data; a third bias unit configured to provide the negative current and the second feedback current corresponding to the high input voltage and the feedback output voltage by using the first negative bias current of the second current supply circuit; and a fourth bias unit configured to provide the negative current and the second feedback current corresponding to the low input voltage and the feedback output voltage by using the second negative bias current of the second current supply circuit.