# US 11,308,253 B2 · Partitioning in post-layout circuit simulation

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- Number: US 11,308,253 B2
- Document ID: US11308253B2
- Status: Granted
- Kind: B2
- Application number: 16/046,957
- Filed: 2018-07-26
- Published: 2019-01-31
- Granted: 2022-04-19
- Earliest claimed: 2017-07-27
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Ningjia Zhu
- Web page: https://patentgrep.com/patent/US11308253B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 2111/04: Constraint-based CAD
- G06F 2111/20: Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
- G06F 2119/06: Power analysis or power optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The independent claims of this patent signify a concise description of embodiments. New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.

## Claims

### Claim 1

A method comprising:
receiving a post-layout circuit netlist comprising a rail block, power nets that do not belong to the rail block, and signal nets; wherein the rail block includes a voltage source, and the power nets drive the signal nets from the rail block;
combining, by a processor, the rail block and the power nets to generate an updated rail block;
partitioning the post-layout circuit netlist including the signal nets and excluding the updated rail block, into signal blocks supplied by the updated rail block; and
applying a circuit simulation to the partitioned signal blocks.

### Claim 2 (depends on 1)

The method of claim 1, wherein partitioning the post-layout circuit netlist into signal blocks comprises:
grouping connected resistors in the signal nets to create a super-network;
analyzing the resistor distribution of the super-network for cut locations;
cutting the super-resistor network at the cut locations to generate sub-nets; and
recording a cut conductance/capacitance maximum value of each of the sub-nets to measure a level of cross-talk.

### Claim 3 (depends on 1)

The method of claim 1, wherein the post-layout circuit netlist results from RC extraction applied to a pre-layout circuit netlist, and partitioning the post-layout circuit netlist into signal blocks comprises:
shorting all resistors in the pre-layout circuit netlist and the post-layout circuit netlist;
recording all instances and their connectivity in the pre-layout circuit netlist;
checking each instance connectivity path of the post-layout circuit netlist against the connectivity in the pre-layout circuit netlist; and
cutting all paths in the post-layout circuit netlist which do not exist in the pre-layout circuit netlist.

### Claim 4 (depends on 1)

The method of claim 1, wherein applying the circuit simulation comprises:
scheduling the signal blocks for simulation in a simulation order that is based on their driver-load relationship or parent-child relationship;
solving the KCL and KVL equations in each of the signal blocks to generate simulation results; and
outputting the simulation results as waveforms.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
performing array optimization in the signal blocks that are memory circuits.

### Claim 6 (depends on 1)

The method of claim 1 further comprising:
after partitioning the post-layout circuit netlist into signal blocks, splitting the updated rail block into the rail block and power nets;
partitioning the power nets into power net blocks which drive different corresponding sub-circuits during the circuit simulation, the sub-circuits comprising the signal blocks.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
selecting a pair of nodes between two power net blocks, wherein the pair of nodes includes one node from one power net block, and a second node from another power net block along the border of the super-network; and
selecting a pair of nodes between two sub-circuit designs, wherein the pair of nodes includes one node from one sub-circuit, and a second node from another sub-circuit.

### Claim 8 (depends on 1)

The method of claim 1 wherein the post-layout circuit netlist results from RC extraction applied to a pre-layout circuit netlist, and partitioning the post-layout circuit netlist into signal blocks results in a same number of signal blocks as a partitioning of the pre-layout circuit netlist.

### Claim 9 (depends on 1)

The method of claim 1 wherein the post-layout circuit netlist results from RC extraction applied to a pre-layout circuit netlist, and partitioning the post-layout circuit netlist into signal blocks comprises cutting the post-layout circuit netlist at same locations as a partitioning of the pre-layout circuit netlist.

### Claim 10

A system comprising:
a memory storing instructions; and
a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
access a shared database storing a pre-layout circuit netlist of an integrated circuit design and a post-layout circuit netlist of the integrated circuit design; the post-layout circuit netlist comprising one or more rail blocks, one or more power nets that do not belong to the rail blocks, and one or more signal nets; wherein the rail blocks includes a voltage source, the power nets drive the signal nets from the rail blocks, and the post-layout circuit netlist comprises parasitic RC circuit elements produced by RC extraction applied to the integrated circuit design;
partition the signal nets into signal blocks supplied by the rail blocks and/or power nets, wherein partitioning into the signal blocks is based on the parasitic RC circuit elements produced by the RC extraction and on a partitioning of the pre-layout circuit netlist; and
apply a circuit simulation to sub-circuits defined by the partitioned signal blocks of the post-layout circuit netlist.

### Claim 11 (depends on 10)

The system of claim 10 wherein the instructions when executed further cause the processor to:
compare the pre-layout circuit netlist and the post-layout circuit netlist; and
apply a circuit simulation to the pre-layout circuit netlist in parallel with applying the circuit simulation to sub-circuits defined by the partitioned signal blocks of the post-layout circuit netlist, wherein the parallel circuit simulations share data.

### Claim 12 (depends on 10)

The system of claim 10 wherein applying the circuit simulations in parallel further comprise performing a dynamic trace between the simulation results of the parallel circuit simulations.

### Claim 13 (depends on 10)

The system of claim 10 wherein the shared database comprises a combination of the pre-layout circuit netlist and the post-layout circuit netlist.

### Claim 14 (depends on 10)

The system of claim 10 wherein the instructions when executed further cause the processor to:
partition the power nets into power net blocks which drive different corresponding sub-circuits during the circuit simulation.

### Claim 15 (depends on 10)

The system of claim 10 wherein partitioning the signal nets into signal blocks results in a same number of signal blocks as the partitioning of the pre-layout circuit netlist.

### Claim 16

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
receive a post-layout circuit netlist of an integrated circuit design; the post-layout circuit netlist comprising one or more rail blocks, one or more power nets that do not belong to the rail blocks, and one or more signal nets; wherein the rail blocks includes a voltage source, the power nets drive the signal nets from the rail blocks, and the post-layout circuit netlist comprises parasitic RC circuit elements produced by RC extraction applied to the integrated circuit design;
partition, by a processor, the signal nets into signal blocks supplied by the rail blocks and/or power nets, wherein partitioning the signal blocks is based on a partitioning of a pre-layout circuit netlist of the integrated circuit design; and
apply a circuit simulation to sub-circuits defined by the partitioned signal blocks.

### Claim 17 (depends on 16)

The non-transitory computer readable medium of claim 16 wherein partitioning the signal nets into signal blocks results in a same number of signal blocks as the partitioning of the pre-layout circuit netlist.

### Claim 18 (depends on 16)

The non-transitory computer readable medium of claim 16 wherein the instructions when executed further cause the processor to:
partition the power nets into power net blocks which drive different corresponding sub-circuits during the circuit simulation.

### Claim 19 (depends on 16)

The non-transitory computer readable medium of claim 16 wherein the pre-layout circuit netlist and the post-layout circuit netlist are stored in a shared database.

### Claim 20 (depends on 19)

The non-transitory computer readable medium of claim 19 wherein partitioning of the pre-layout circuit netlist and partitioning of the post-layout circuit netlist are also stored in the shared database.