# US 11,308,217 B2 · Randomized execution countermeasures against fault injection attacks during boot of an embedded device

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- Number: US 11,308,217 B2
- Document ID: US11308217B2
- Status: Granted
- Kind: B2
- Application number: 16/864,621
- Filed: 2020-05-01
- Published: 2020-08-13
- Granted: 2022-04-19
- Earliest claimed: 2017-08-31
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Madan Srinivas; Sachin Billore; Kavitha Malarvizhi; Amritpal Mundra
- Web page: https://patentgrep.com/patent/US11308217B2

## CPC

- G06F 21/575: {Secure boot}
- G06F 1/24: Resetting means
- G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57)
- G06F 21/566: {Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities}
- G06F 2221/034: Test or assess a computer or a system
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An embedded device is provided that is configured to randomize execution time of a boot process of the embedded device performed responsive to a reset signal, wherein reset release time is nondeterministic. The embedded device may include a randomizer component configured to generate a timeout signal after a random interval, wherein to randomize execution time, the embedded device is further configured to execute a first portion of a reset process, signal the randomizer component to generate the timeout signal after a first random interval, wait for the timeout signal, and execute a second portion of the reset process responsive to the timeout signal.

## Claims

### Claim 1

An apparatus, comprising:
a randomizer component;
a control component coupled to the randomizer component and configured to:
execute a portion of a reset process;
pause the reset process; and
receive a timeout signal from the randomizer component; and
continue the reset process after receiving the timeout signal from the randomizer component.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising a hardware random number generator, and wherein the randomizer component comprises timer circuitry and circuitry to initialize the hardware random number generator and to obtain a random number from the hardware random number generator to seed the timer circuitry.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the control component is further configured to signal the randomizer component to generate the timeout signal after a second random interval after a second portion is executed.

### Claim 4 (depends on 1)

The apparatus of claim 1, further comprising a boot read-only-memory (ROM) configured to store boot code, wherein initiation of execution of the boot code after reset release is randomized.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the boot code comprises a random delay between a first boot code function and a second boot code function, wherein execution time of a security function is nondeterministic.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the random delay is implemented as a delay loop that is executed for a randomly selected number of times.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the boot code is configured to randomize an order of execution of independent boot functions.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising a control component coupled to the randomizer component and configured to signal the randomizer component to start operation at selected points in the reset process.

### Claim 9 (depends on 1)

The apparatus of claim 1, further comprising a boot read-only-memory (ROM) configured to store a plurality of boot codes for the reset process, wherein initiation of the rest process includes executing a first boot code after the reset release, which is randomized, the reset process comprises a random delay between executing the first boot code and executing a second boot code such that execution time of the reset process is nondeterministic.

### Claim 10

A method, comprising:
executing a portion of a reset process of a boot process for an electronic apparatus responsive to a reset signal;
pausing the reset process;
receiving a timeout signal from a randomizer component; and
continuing the reset process after the timeout signal is received.

### Claim 11 (depends on 10)

The method of claim 10, wherein the reset process is a power on reset process.

### Claim 12 (depends on 10)

The method of claim 10, further comprising initializing a hardware random number generator and seeding timer circuitry based on a random number obtained from the hardware random number generator.

### Claim 13 (depends on 10)

The method of claim 10, further comprising randomizing initiation of execution of boot code after reset release.

### Claim 14 (depends on 13)

The method of claim 13, further comprising executing a random delay between a first boot code function and a second boot code function, wherein execution time of a security function is nondeterministic.

### Claim 15 (depends on 14)

The method of claim 14, wherein the random delay is implemented as a delay loop that is executed for a randomly selected number of times.

### Claim 16 (depends on 13)

The method of claim 13, further comprising randomizing an order of execution of independent boot functions.