# US 11,308,010 B2 · Memory system having memories of different capacities

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- Number: US 11,308,010 B2
- Document ID: US11308010B2
- Status: Granted
- Kind: B2
- Application number: 16/856,049
- Filed: 2020-04-23
- Published: 2020-11-19
- Granted: 2022-04-19
- Earliest claimed: 2019-05-15
- Assignees: Realtek Semiconductor Corp.
- Applicants: Realtek Semiconductor Corp.
- Inventors: Ya-Min Chang
- Web page: https://patentgrep.com/patent/US11308010B2

## CPC

- G06F 13/1694: {Configuration of memory controller to different memory types}
- G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 12/1054: {the data cache being concurrently physically addressed}
- G06F 12/1063: {the data cache being concurrently virtually addressed}
- G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence)
- G06F 13/1678: {using bus width}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 2212/1041: Resource optimization
- G06F 2212/656: Address space sharing
- G06F 2212/657: Virtual address space management
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory system includes a memory controller, a first memory, and a second memory. The memory controller has a command address port, a chip select port, a first data port, and a second data port. The first memory is coupled to the command address port, the chip select port, and the first data port, and the second memory is coupled to the command address port, the chip select port, and the second data port. The capacity of the second memory is greater than the capacity of the first memory. The memory controller controls the first memory and the second memory simultaneously through the command address port and the chip select port.

## Claims

### Claim 1

A memory system comprising:
a memory controller having a command address port, a chip select port, a first data port, and a second data port;
a first memory coupled to the command address port, the chip select port, and the first data port; and
a second memory coupled to the command address port, the chip select port, and the second data port;
wherein:
a capacity of the second memory is greater than a capacity of the first memory;
the memory controller controls the first memory and the second memory simultaneously through the command address port and the chip select port;
the second memory comprises a first physical memory segment and a second physical memory segment;
the first physical memory segment of the second memory and the first memory are corresponding to a first virtual memory segment; and
the second physical memory segment of the second memory is corresponding to a second virtual memory segment.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the first memory and the second memory are synchronous dynamic random-access memories (SDRAM).

### Claim 3 (depends on 1)

The memory system of claim 1, wherein:
the memory system outputs output data corresponding to the first virtual memory segment with a first effective bandwidth, and outputs output data corresponding to the second virtual memory segment with a second effective bandwidth; and
the first effective bandwidth is greater than the second effective bandwidth.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein the first physical memory segment of the second memory has a same capacity as the first memory.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the first physical memory segment of the second memory has a same capacity as the second physical memory segment of the second memory.

### Claim 6 (depends on 1)

The memory system of claim 1, wherein when the memory system reads data corresponding to the first virtual memory segment, the memory controller is configured to:
perform a reading operation to the first memory and the second memory according to a corresponding address;
combine first reading data received from the first memory through the first data port and second reading data received from the second memory through the second data port to generate output data; and
output the output data.

### Claim 7 (depends on 6)

The memory system of claim 6, wherein the memory controller determines the corresponding address to be corresponding to the first virtual memory segment or the second virtual memory segment according to a most significant bit of the corresponding address.

### Claim 8 (depends on 1)

The memory system of claim 1, wherein when the memory system reads data corresponding to the second virtual memory segment, the memory controller is configured to:
perform a reading operation to the second memory according to a corresponding address;
take reading data received from the second memory through the second data port as output data; and
output the output data.

### Claim 9 (depends on 1)

The memory system of claim 1, wherein a data bandwidth of the first memory and a data bandwidth of the second memory are the same.

### Claim 10

A method for operating a memory system, the memory system comprising a first memory and a second memory, a capacity of the second memory being greater than a capacity of the first memory, the second memory comprising a first physical memory segment and a second physical memory segment, the first physical memory segment of the second memory and the first memory being corresponding to a first virtual memory segment, the second physical memory segment of the second memory being corresponding to a second virtual memory segment, and the method comprising:
performing a reading operation to the first memory and the second memory according to a corresponding address;
the first memory outputting first reading data;
the second memory outputting second reading data; and
outputting output data according to whether the corresponding address is corresponding to the first virtual memory segment or the second virtual memory segment.

### Claim 11 (depends on 10)

The method of claim 10, wherein outputting the output data according to whether the corresponding address is corresponding to the first virtual memory segment or the second virtual memory segment comprises:
when the corresponding address is corresponding to the first virtual memory segment, combining the first reading data and the second reading data as the output data.

### Claim 12 (depends on 10)

The method of claim 10, wherein outputting the output data according to whether the corresponding address is corresponding to the first virtual memory segment or the second virtual memory segment comprises:
when the corresponding address is corresponding to the second virtual memory segment, taking the second reading data as the output data.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first memory and the second memory are synchronous dynamic random-access memories (SDRAM).

### Claim 14 (depends on 10)

The method of claim 10, wherein:
when the corresponding address is corresponding to the first virtual memory segment, the memory system outputs the output data with a first effective bandwidth;
when the corresponding address is corresponding to the second virtual memory segment, the memory system outputs the output data with a second effective bandwidth; and
the first effective bandwidth is greater than the second effective bandwidth.

### Claim 15 (depends on 10)

The method of claim 10, wherein the first physical memory segment of the second memory has a same capacity as the first memory.

### Claim 16 (depends on 10)

The method of claim 10, wherein the first physical memory segment of the second memory has a same capacity as the second physical memory segment of the second memory.

### Claim 17 (depends on 10)

The method of claim 10, wherein a data bandwidth of the first memory and a data bandwidth of the second memory are the same.

### Claim 18 (depends on 10)

The method of claim 10, further comprising:
determining the corresponding address to be corresponding to the first virtual memory segment or the second virtual memory segment according to a most significant bit of the corresponding address.