# US 11,308,009 B2 · Interface for memory readout from a memory component in the event of fault

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- Number: US 11,308,009 B2
- Document ID: US11308009B2
- Status: Granted
- Kind: B2
- Application number: 16/548,714
- Filed: 2019-08-22
- Published: 2020-02-13
- Granted: 2022-04-19
- Earliest claimed: 2015-10-07
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. Ware; Kenneth L. Wright
- Web page: https://patentgrep.com/patent/US11308009B2

## CPC

- G06F 13/1684: {using multiple buses}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 11/0784: {Routing of error reports, e.g. with a specific transmission path or data flow}
- G06F 11/2007: {using redundant communication media}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

## Claims

### Claim 1

A method of operation in an integrated circuit (IC) memory die having a memory core, the method comprising:
accessing the memory core during a normal mode of operation with a primary interface that is formed in the IC memory die, the primary interface including data input/output (I/O) circuitry and control/address (C/A) input circuitry;
detecting a fault with an error code;
initiating a fault mode of operation in response to the detected fault; and
accessing the memory core during the fault mode of operation with a secondary interface that is formed in the IC memory die.

### Claim 2 (depends on 1)

The method of claim 1, wherein during the fault mode of operation, the method further comprises:
disabling the primary interface; and
enabling the secondary interface.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
accessing the memory core during the normal mode of operation with the primary interface involves data transfers of a first data width; and
wherein accessing the memory core during the fault mode of operation with the secondary interface involves data transfers of a second width that is less than the first data width.

### Claim 4 (depends on 3)

The method of claim 3, wherein accessing the memory core during the fault mode of operation with the secondary interface comprises:
transferring serialized signals via the secondary interface.

### Claim 5 (depends on 1)

The method of claim 1, wherein the detecting the fault with the error code comprises:
detecting the fault with an error detection correction (EDC) code.

### Claim 6 (depends on 1)

The method of claim 1, wherein the IC memory die enters the fault mode of operation in response to the error code indicating a fault in the primary interface.

### Claim 7 (depends on 6)

The method of claim 6, wherein the initiating the fault mode of operation in response to the detected fault in the primary interface comprises:
initiating the fault mode of operation in response to the detected fault being associated with the data I/O circuitry.

### Claim 8 (depends on 6)

The method of claim 6, wherein the initiating the fault mode of operation in response to the detected fault in the primary interface comprises:
initiating the fault mode of operation in response to the detected fault being associated with the C/A input circuitry.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
during the fault mode,
accessing data stored in the memory core; and
transferring the accessed data off-chip.

### Claim 10 (depends on 9)

The method of claim 9, wherein the transferring comprises:
transferring the accessed data off-chip to spare storage.

### Claim 11 (depends on 10)

The method of claim 10, wherein the transferring comprises:
transferring the accessed data off-chip to a spare memory component.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
using the secondary interface to communicate with a remote secondary interface of a second IC memory component via a serial bus.

### Claim 13

A method of operation in a memory module, the memory module including a primary databus connector and multiple IC memory die coupled to the primary databus connector via respective primary interfaces, the memory module including a secondary data bus coupled to respective secondary interfaces of the multiple IC memory die, each IC memory die including a memory core, wherein the method comprising:
for each of the multiple IC memory die,
accessing the memory core during a normal mode of operation with a corresponding primary interface that is formed in the IC memory die; detecting a fault with an error code;
initiating a fault mode of operation in response to the detected fault; and
accessing the memory core during the fault mode of operation with a corresponding secondary interface that is formed in the IC memory die.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
routing data transfers along the secondary data bus in a daisy-chained manner.

### Claim 15 (depends on 13)

The method of claim 13, wherein at least one of the multiple IC memory die comprises a spare memory die, and wherein the method further comprises:
receiving data from one of the multiple IC memory die associated with the fault during the fault mode of operation.

### Claim 16 (depends on 13)

The method of claim 13, wherein during the fault mode of operation for each of the multiple IC memory die, the method comprising:
enabling the secondary interface to carry out data transfer operations while disabling the primary interface.

### Claim 17

A method of operation in a memory system, the memory system including a first memory module including a primary databus connector for coupling to a memory controller and multiple IC memory die coupled to the primary databus connector via respective primary interfaces, the first memory module including a secondary data bus coupled to respective secondary interfaces of the multiple IC memory die, each IC memory die including a memory core, wherein the method comprising:
for each of the multiple IC memory die,
accessing the memory core during a normal mode of operation with a corresponding primary interface that is formed in the IC memory die;
detecting a fault with an error code;
initiating a fault mode of operation in response to the detected fault; and
accessing the memory core during the fault mode of operation with a corresponding secondary interface that is formed in the IC memory die.

### Claim 18 (depends on 17)

The method of claim 17, wherein each of the multiple IC memory die further includes repair logic, and wherein the method further comprises:
controlling the secondary interface via the repair logic.

### Claim 19 (depends on 17)

The method of claim 17, wherein the method further comprises:
controlling the secondary interface via the memory controller.

### Claim 20 (depends on 17)

The method of claim 17, wherein the system includes a second memory module coupled to the memory controller via the primary databus, and wherein the method further comprises:
operating the first memory module and the second memory module in a lockstep mode of operation.