# US 11,308,006 B2 · Memory rank design for a memory channel that is optimized for graph applications

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- Number: US 11,308,006 B2
- Document ID: US11308006B2
- Status: Granted
- Kind: B2
- Application number: 16/833,322
- Filed: 2020-03-27
- Published: 2020-07-23
- Granted: 2022-04-19
- Earliest claimed: 2020-03-27
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Byoungchan Oh; Sai Dheeraj Polagani; Joshua B. Fryman
- Web page: https://patentgrep.com/patent/US11308006B2

## CPC

- G06F 13/1668: {Details of memory controller}
- G06F 12/0879: Burst mode
- G06F 13/4239: {with asynchronous protocol}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 2029/0411: {Online error correction}
- G11C 2207/2254: Calibration
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus is described. The apparatus includes a rank of memory chips to couple to a memory channel. The memory channel is characterized as having eight transfers of eight bits of raw data per burst access. The rank of memory chips has first, second and third X4 memory chips. The X4 memory chips conform to a JEDEC dual data rate (DDR) memory interface specification. The first and second X4 memory chips are to couple to an eight bit raw data portion of the memory channel's data bus. The third X4 memory chip to couple to an error correction coding (ECC) information portion of the memory channel's data bus.

## Claims

### Claim 1

An apparatus, comprising:
a rank of memory chips to couple to a memory channel, the memory channel characterized as having eight transfers of eight bits of raw data per burst access, the rank of memory chips comprising first, second and third X4 memory chips, the X4 memory chips conforming to a JEDEC dual data rate (DDR) memory interface specification, the first and second X4 memory chips are to couple to an eight bit raw data portion of the memory channel's data bus, the third X4 memory chip to couple to an error correction coding (ECC) information portion of the memory channel's data bus.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein the X4 memory chips are X4 DDR4 memory chips.

### Claim 3 (depends on 2)

The apparatus of claim 2 wherein the rank of memory chips is disposed on a dual in-line memory module.

### Claim 4 (depends on 1)

The apparatus of claim 1 wherein the X4 memory chips are X4 DDR5 memory chips.

### Claim 5 (depends on 4)

The apparatus of claim 4 wherein the eight data transfers per burst access are to be performed in a chop mode.

### Claim 6 (depends on 4)

The apparatus of claim 4 wherein the rank of memory chips is disposed on a dual in-line memory module.

### Claim 7 (depends on 1)

The apparatus of claim 1 wherein the ECC information portion of the memory channel's data bus is to transport an entire symbol of ECC information across data pins of the third X4 memory chip.

### Claim 8 (depends on 1)

The apparatus of claim 1 wherein the ECC information portion of the memory channel's data bus is to transport an entire symbol of ECC information over a single data pin of the third X4 memory chip.

### Claim 9

A computing system, comprising:
a plurality of CPU processing cores;
a graphics processing unit;
a memory controller, a memory channel emanating from the memory controller, the memory channel characterized as having eight transfers of eight bits of raw data per burst access, a memory module coupled to the memory channel, the memory module comprising a rank of memory chips, the rank of memory chips comprising first, second and third X4 memory chips, the X4 memory chips conforming to a JEDEC dual data rate (DDR) memory interface specification, the first and second X4 memory chips to couple to an eight bit raw data portion of the memory channel's data bus, the third X4 memory chip to couple to an error correction coding (ECC) information portion of the memory channel's data bus.

### Claim 10 (depends on 9)

The apparatus of claim 9 wherein the X4 memory chips are X4 DDR4 memory chips.

### Claim 11 (depends on 10)

The apparatus of claim 10 wherein the memory module is a dual in-line memory module.

### Claim 12 (depends on 9)

The apparatus of claim 9 wherein the X4 memory chips are X4 DDR5 memory chips.

### Claim 13 (depends on 12)

The apparatus of claim 12 wherein the eight data transfers per burst access are to be performed in a chop mode.

### Claim 14 (depends on 13)

The apparatus of claim 13 wherein the memory module is a dual in-line memory module.

### Claim 15

A memory controller, comprising:
an interface to communicate with a memory chip that conforms to a JEDEC dual data rate (DDR) memory interface specification, the memory controller comprising logic circuitry to:
access memory chips that conform to the JEDEC DDR interface specification with eight transfers of eight bits of raw data and four bits of ECC information per burst access;
calculate ECC information from a burst access's raw data with a symbol orientation that is based on a manufacturer of the memory chips.

### Claim 16 (depends on 15)

The memory controller of claim 15 wherein a first ECC symbol orientation comprises orienting symbols length-wise such that a single symbol is transferred over a single data pin of any of the memory chips.

### Claim 17 (depends on 16)

The memory controller of claim 16 wherein a second ECC symbol orientation comprises orienting symbols cross-wise such that a single symbol is transferred over four data pins of any of the memory chips.

### Claim 18 (depends on 15)

The memory controller of claim 15 wherein the eight transfers are performed in a chop mode.

### Claim 19 (depends on 15)

The memory controller of claim 15 wherein the memory controller comprises configuration register space to establish a particular one of multiple available symbol orientations.

### Claim 20 (depends on 15)

The memory module of claim 15 wherein the memory controller comprises another interface to communicate with another memory chip according to a burst process that transfers a CPU cache line.