# US 11,308,005 B2 · Cache coherent, high-throughput input/output controller > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,308,005 B2 - Document ID: US11308005B2 - Status: Granted - Kind: B2 - Application number: 16/022,327 - Filed: 2018-06-28 - Published: 2019-02-07 - Granted: 2022-04-19 - Earliest claimed: 2018-06-28 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Mrigank Shekhar - Web page: https://patentgrep.com/patent/US11308005B2 ## CPC - G06F 13/1668: {Details of memory controller} - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 12/0815: Cache consistency protocols - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising} - G06F 2213/0026: PCI express - G06F 2213/0032: Serial ATA [SATA] - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Input/output controllers and methods of operation thereof that may provide high-throughput data services to processing circuitry is described. The input/output controllers may make use of cache coherent data links and/or switch fabric to improve data throughput and decrease latency in the communication. ## Claims ### Claim 1 An integrated circuit comprising: an interface configured to couple to processing circuitry, wherein the interface comprises a cache memory and wherein the interface is configured to couple to the processing circuitry using a cache coherent data link that comprises a cache coherent protocol; an input/output controller configured to couple to an input/output device; functional circuitry configured to perform at least a first data operation; and switch fabric configured to route data between the cache memory of the interface and the functional circuitry, the interface and the input/output controller, or the functional circuitry and the input/output controller. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the first data operation comprises a compression operation, a decompression operation, an encryption operation, a decryption operation, an error checking operation, or a mathematical transformation, or any combination thereof. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the integrated circuit comprises a programmable fabric that comprises the interface, the input/output controller, the functional circuitry, or the switch fabric, or any combination thereof. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the interface comprises a Peripheral Component Interface Express (PCIe) interface. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the input/output controller comprises a non-volatile memory extended (NVMe) controller, and wherein the input/output device comprises a non-volatile memory device. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the switch fabric is coupled to the cache memory of the interface via a second cache coherent data link that comprises the cache coherent protocol. ### Claim 7 (depends on 6) The integrated circuit of claim 6, comprising a second interface configured to couple to the processing circuitry. ### Claim 8 An electronic device, comprising: a processor; a storage device; and an integrated circuit comprising: an interface coupled to the processor; a storage controller coupled to the storage device; functional circuitry configured to perform a first data operation; and switch fabric configured to route data between the interface, the storage device, and the functional circuitry. ### Claim 9 (depends on 8) The electronic device of claim 8, wherein the storage device comprises a hard disk (HD), a solid-state drive (SSD) disk, or a random access memory disk (RAMdisk), or any combination thereof. ### Claim 10 (depends on 8) The electronic device of claim 8 wherein the storage controller comprises a non-volatile memory express (NVMe) controller, a serial AT adaptor (SATA) controller, or both. ### Claim 11 (depends on 8) The electronic device of claim 8, comprising a first data link coupling the integrated circuit to the processor and a second data link coupling the integrated circuit to the storage device, wherein a first bandwidth of the first data link is higher than a bandwidth of the second data link, wherein the functional circuitry is configured to perform a compression operation, and decompression operation. ### Claim 12 (depends on 11) The electronic device of claim 11, wherein the processor is configured to write data to the storage device by: sending the data to the interface; routing, using the switch fabric, the data from the interface to the functional circuitry; requesting performance of the compression operation over the data in the functional circuitry; and routing, using the switch fabric, the data from the functional circuitry to the storage controller. ### Claim 13 (depends on 11) The electronic device of claim 11, wherein the processor is configured to read data from the storage device by: requesting data from the storage device via the storage controller; routing, using the switch fabric, the data from the storage controller to the functional circuitry; requesting performance of the decompression operation over the data in the functional circuitry; and routing, using the switch fabric, the data from the functional circuitry to the interface. ### Claim 14 (depends on 8) The electronic device of claim 8, wherein the functional circuitry is configured to perform an error detection or error correction operation. ### Claim 15 (depends on 8) The electronic device of claim 8, comprising a cache coherent domain comprising the processor and a cache of the interface. ### Claim 16 (depends on 15) The electronic device of claim 15, comprising an operating memory coupled to the processor, wherein the cache coherent domain comprises the operating memory. ### Claim 17 (depends on 8) The electronic device of claim 8, comprising a system on chip (SoC) that comprises the processor and the integrated circuit. ### Claim 18 (depends on 8) The electronic device of claim 8, wherein the integrated circuit comprises a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a hybrid device comprising hardened circuitry and programmable fabric. ### Claim 19 A method comprising: sending, from a processor, data to an interface of an integrated circuit using a first data link that comprises a first bandwidth; requesting a switch fabric of the integrated circuit to route the data to functional circuitry of the integrated circuit; requesting, from the functional circuitry, compression of the data; receiving, from the integrated circuit, a notification of completion of the compression of the data by the functional circuitry; and requesting the switch fabric of the integrated circuit to route the data from the functional circuitry to a storage device coupled to the integrated circuit using a second data link, wherein the second data link comprises a second bandwidth that is smaller than the first bandwidth. ### Claim 20 (depends on 19) The method of claim 19, comprising requesting from the functional circuitry, an error checking operation of the data.