# US 11,307,999 B2 · Data cache segregation for spectre mitigation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,999 B2 - Document ID: US11307999B2 - Status: Granted - Kind: B2 - Application number: 16/870,131 - Filed: 2020-05-08 - Published: 2020-08-27 - Granted: 2022-04-19 - Earliest claimed: 2018-04-12 - Assignees: Sony Interactive Entertainment Inc. - Applicants: Sony Interactive Entertainment Inc. - Inventors: Paul T. Robinson - Web page: https://patentgrep.com/patent/US11307999B2 ## CPC - G06F 12/1458: {by checking the subject access rights} - G06F 21/74: operating in dual or compartmented mode, i.e. at least one secure mode - G06F 12/084: with a shared cache - G06F 12/0848: {Partitioned cache, e.g. separate instruction and operand caches} - G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) - G06F 21/52: during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} - G06F 2212/1052: Security improvement - G06F 2212/603: of operating mode, e.g. cache mode or local memory mode - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The data cache of a processor is segregated by execution mode, eliminating the danger of certain malware by no longer sharing the resource. Kernel-mode software can adjust the relative size of the two portions of the data cache, to dynamically accommodate the data-cache needs of varying workloads. ## Claims ### Claim 1 A device comprising: at least one central processing unit (CPU) assembly comprising: at least a first CPU thread; at least a first cache accessible to the first CPU thread; plural signal lines for communicating data between the first CPU thread and the first cache, the CPU thread being configured to expose a value on at least a first signal line of the plural signal lines, a first value on the first signal line indicating a memory address associated with first mode cache, a second value on the first signal line indicating a memory address associated with second mode cache, wherein data associated with a second mode application can be written to and read from second mode cache such that no second mode application can detect operations of the first mode cache. ### Claim 2 (depends on 1) The device of claim 1, wherein data associated with a first mode application can be written to and read from first mode cache. ### Claim 3 (depends on 1) The device of claim 1, wherein the second mode cache and first mode cache are virtual partitions of the first cache. ### Claim 4 (depends on 1) The device of claim 1, comprising a second cache, wherein the second mode cache and first mode cache are established by the first cache and second cache, respectively. ### Claim 5 (depends on 1) The device of claim 1, comprising third cache, wherein data associated with a second mode application can be written to and read from second mode cache of the third cache such that no second mode application can detect operations in the first mode with the third cache. ### Claim 6 (depends on 3) The device of claim 3, wherein respective sizes of the second mode cache and first mode cache change during CPU operation. ### Claim 7 (depends on 6) The device of claim 6, wherein the sizes change according to at least one parameter under control of first mode software. ### Claim 8 (depends on 6) The device of claim 6, wherein the sizes change according to data storage amount in at least one of the second mode cache and first mode cache. ### Claim 9 (depends on 6) The device of claim 6, wherein the sizes change according to data input/output rate in at least one of the second mode cache and first mode cache. ### Claim 10 (depends on 1) The device of claim 1, wherein the CPU assembly comprises a first CPU core and the device comprises at least a second CPU core in a CPU package, and the first and second CPU cores share at least one cache. ### Claim 11 An apparatus comprising: at least one central processing unit (CPU) core comprising: at least a first CPU thread; cache assembly accessible to the first CPU thread; and plural signal lines for communicating data between the first CPU thread and the cache assembly, the CPU thread being configured to expose a value on at least a first signal line of the plural signal lines, a first value on the first signal line indicating a memory address associated with a first mode cache of the cache assembly, a second value on the first signal line indicating a memory address associated with a second mode cache of the cache assembly. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the cache assembly comprises a single physical cache portioned into the second mode cache and first mode cache. ### Claim 13 (depends on 11) The apparatus of claim 11, wherein the cache assembly comprises a first physical cache establishing the second mode cache and a second physical cache establishing the first mode cache. ### Claim 14 (depends on 11) The apparatus of claim 11, wherein during CPU operation in a second mode, second mode applications are allowed to execute input/output operations to the second mode cache, with second mode applications being disallowed from accessing first mode cache including data eviction from first mode cache. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein programs operating in a first mode are allowed to access first mode cache for writing first mode data. ### Claim 16 (depends on 11) The apparatus of claim 11, wherein data associated with a second mode application can be written to and read from second mode cache such that no second mode application can detect operations of the first mode cache. ### Claim 17 (depends on 11) The apparatus of claim 11, comprising third cache, wherein data associated with a second mode application can be written to and read from second mode cache of the third cache such that no second mode application can detect operations in the first mode with the third cache. ### Claim 18 (depends on 11) The apparatus of claim 11, wherein the CPU core is a first CPU core and the apparatus comprises at least a second CPU core in a CPU package, and the first and second CPU cores share an L3 cache. ### Claim 19 A method, comprising: segregating data cache of a processor according to execution mode, execution mode comprising first mode and second mode; and exposing a value on at least a first signal line of plural signal lines, a first value on the first signal line indicating a memory address associated with the first mode, a second value on the first signal line indicating a memory address associated with the second mode. ### Claim 20 (depends on 19) The method of claim 19, comprising using kernel-mode software to adjust relative sizes of the first mode cache and second mode cache.