# US 11,307,988 B2 · Configurable cache for multi-endpoint heterogeneous coherent system

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- Number: US 11,307,988 B2
- Document ID: US11307988B2
- Status: Granted
- Kind: B2
- Application number: 16/653,263
- Filed: 2019-10-15
- Published: 2020-04-16
- Granted: 2022-04-19
- Earliest claimed: 2018-10-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Kai Chirca; Matthew David Pierson
- Web page: https://patentgrep.com/patent/US11307988B2

## CPC

- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/064: {Management of blocks}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30123: {according to context, e.g. thread buffers}
- G06F 9/3897: {with adaptable data path}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/5016: {the resource being the memory}
- G06F 12/0607: {Interleaved addressing}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/084: with a shared cache
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0857: {by multiple requestors}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/10: Address translation
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine}
- G06F 13/1642: {with request queuing}
- G06F 13/1663: {Access to shared memory}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- H03M 13/015: {Simulation or testing of codes, e.g. bit error rate [BER] measurements}
- H03M 13/098: {using single parity bit}
- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- H03M 13/276: {Interleaving address generation}
- H03M 13/2785: {Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location}
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible
- G06F 12/0851: {Cache with interleaved addressing}
- G06F 12/0862: with prefetch
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1048: Scalability
- G06F 2212/304: In main memory subsystem
- G06F 2212/452: Instruction code
- G06F 2212/6024: History based prefetching
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

## Claims

### Claim 1

A device comprising:
a memory bank including:
data portions of a first way group including:
a data portion of a first way of the first way group; and
a data portion of a second way of the first way group; and
data portions of a second way group;
a configuration register; and
a controller configured to determine:
a first way identifier for the first way based on a first randomly generated allocation pointer, a first AND mask, and a first OR mask;
a second way identifier for the second way based on the first randomly generated allocation pointer, a second AND mask, and a second OR mask;
a first group identifier for the first way group based on a set of most significant bits of the first randomly generated allocation pointer; and
a second group identifier for the second way group based on a set of most significant bits of a second randomly generated allocation pointer;
wherein the controller is configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a snoop filter bank including:
a snoop data portion of the first way of the first way group; and
a snoop data portion of the second way of the first way group; and
a cache tag bank including:
a cache tag data portion of the first way of the first way group, the snoop data portion of the first way; and
a cache tag data portion of the second way of the first way group.

### Claim 3 (depends on 2)

The device of claim 2, further comprising an interface configured to connect to a processor, wherein the cache tag data portion of the first way of the first way group is configured to store a cache tag associated with an address accessed by the processor, and wherein the snoop data portion of the first way of the first way group is configured to store a snoop state indicating that the processor includes a cached value for the cache tag.

### Claim 4 (depends on 3)

The device of claim 3, wherein, in response to allocating the data portion of the first way of the first way group to the data cache, the controller is configured to store a cached value associated with the cache tag in the data portion of the first way of the first way group.

### Claim 5 (depends on 4)

The device of claim 4, wherein the controller is configured to overwrite a portion of the cached value in response to receiving a command to write a new value, including fewer bits than the cached value, to the cache tag.

### Claim 6 (depends on 3)

The device of claim 3, wherein, in response to allocating the data portion of the first way of the first way group to the addressable memory space, the controller is configured to respond to read and write requests indicating an address of the data portion of the first way of the first way group.

### Claim 7 (depends on 3)

The device of claim 3, further including:
an interconnect connected to the interface and to the configuration register; and
a data routing unit configured to initiate data transfer requests based on data stored in the configuration register.

### Claim 8 (depends on 1)

The device of claim 1, wherein the controller is configured to allocate the first way group to a real-time priority or to a non-real-time priority based on a real-time setting in the configuration register.

### Claim 9

A system comprising:
multi-core shared memory controller (MSMC) including:
a processor interface;
an external memory interface;
a memory bank including:
data portions of a first way group including:
a data portion of a first way of the first way group; and
a data portion of a second way of the first way group; and
data portions of a second way group;
a configuration register; and
a controller configured to determine:
a first way identifier for the first way based on a first randomly generated allocation pointer, a first AND mask, and a first OR mask;
a second way identifier for the second way based on the first randomly generated allocation pointer, a second AND mask, and a second OR mask;
a first group identifier for the first way group based on a set of most significant bits of the first randomly generated allocation pointer; and
a second group identifier for the second way group based on a set of most significant bits of a second randomly generated allocation pointer;
wherein the controller is configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache;
a processor package connected to the processor interface; and
an external memory device connected to the external memory interface.

### Claim 10 (depends on 9)

The system of claim 9, wherein the MSMC further includes:
a snoop filter bank including:
a snoop data portion of the first way of the first way group; and
a snoop data portion of the second way of the first way group; and
a cache tag bank including:
a cache tag data portion of the first way of the first way group, the snoop data portion of the first way; and
a cache tag data portion of the second way of the first way group.

### Claim 11 (depends on 10)

The system of claim 10, wherein the cache tag data portion of the first way of the first way group is configured to store a cache tag associated with an address accessed by the processor, and wherein the snoop data portion of the first way of the first way group is configured to store a snoop state indicating that the processor includes a cached value for the cache tag.

### Claim 12 (depends on 11)

The system of claim 11, wherein, in response to allocating the data portion of the first way of the first way group to the data cache, the controller is configured to store a cached value associated with the cache tag in the data portion of the first way of the first way group.

### Claim 13 (depends on 12)

The system of claim 12, wherein the controller is configured to overwrite a portion of the cached value in response to receiving a command to write a new value, including fewer bits than the cached value, to the cache tag.

### Claim 14 (depends on 11)

The system of claim 11, wherein, in response to allocating the data portion of the first way of the first way group to the addressable memory space, the controller is configured to respond to read and write requests indicating an address of the data portion of the first way of the first way group.

### Claim 15 (depends on 11)

The system of claim 11, wherein the MSMC further includes:
an interconnect connected to the interface and to the configuration register; and
a data routing unit configured to initiate data transfer requests based on data stored in the configuration register.

### Claim 16 (depends on 9)

The system of claim 9, wherein the controller is configured to allocate the first way group to a real-time priority or to a non-real-time priority based on a real-time setting in the configuration register.

### Claim 17

A method comprising:
receiving, at a controller of a multi-core shared memory controller (MSMC), a configuration setting, the MSMC including a memory bank including:
data portions of a first way group including:
a data portion of a first way of the first way group; and
a data portion of a second way of the first way group; and
data portions of a second way group; and
determining, by the controller, a first way identifier for the first way based on a first randomly generated allocation pointer, a first AND mask, and a first OR mask, a second way identifier for the second way based on the first randomly generated allocation pointer, a second AND mask, and a second OR mask, a first group identifier for the first way group based on a set of most significant bits of the first randomly generated allocation pointer, and a second group identifier for the second way group based on a set of most significant bits of a second randomly generated allocation pointer;
allocating, at the controller, the first way and the second way to one of an addressable memory space and a data cache based on the configuration setting.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first way is allocated to the data cache, the method further comprising:
receiving, from a processor connected to the MSMC, a read request for a data value at a memory address;
retrieving the data value from the memory address;
storing the data value in the data portion of the first way;
storing a cache tag associated with the memory address in a cache tag data portion of the first way included in a cache tag bank; and
storing a snoop state in a snoop state portion of the first way included in a snoop filter bank.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
receiving a request to write to a second value to an address associated with the cache tag, the second value including fewer bits than the data value; and
overwriting a first segment of the data value with the second value while maintaining a second segment of the data value in the data portion of the first way.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
receiving an updated configuration setting allocating the first way to the addressable memory space; and
allocating the first way to the addressable memory space.