# US 11,307,987 B2 · Tag update bus for updated coherence state

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- Number: US 11,307,987 B2
- Document ID: US11307987B2
- Status: Granted
- Kind: B2
- Application number: 16/882,305
- Filed: 2020-05-22
- Published: 2020-11-26
- Granted: 2022-04-19
- Earliest claimed: 2019-05-24
- Assignees: Texas Instmments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Abhijeet Ashok Chachad; David Matthew Thompson; Naveen Bhoria; Peter Michael Hippleheuser
- Web page: https://patentgrep.com/patent/US11307987B2

## CPC

- G06F 12/0811: with multilevel cache hierarchies
- G06F 9/3004: {to perform operations on memory}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/30079: {Pipeline control instructions, e.g. multicycle NOP}
- G06F 9/3867: {using instruction pipelines}
- G06F 9/467: {Transactional memory (G06F9/528 takes precedence)}
- G06F 9/544: {Buffers; Shared memory; Pipes}
- G06F 9/546: {Message passing systems or structures, e.g. queues}
- G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)}
- G06F 11/3055: {Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16)}
- G06F 12/0808: with cache invalidating means (G06F12/0815 takes precedence)
- G06F 12/0815: Cache consistency protocols
- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/084: with a shared cache
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 13/1668: {Details of memory controller}
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/608: Details relating to cache mapping
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

## Claims

### Claim 1

A method, comprising:
receiving, by a level two (L2) controller, a message from a level one (L1) controller over a tag update bus separate from a transaction bus between the L2 controller and the L1 controller, the message comprising a valid signal, an address, and a coherence state; and
in response to the valid signal being asserted:
identifying, by the L2 controller, an entry in a shadow L1 main cache or a shadow L1 victim cache having an address corresponding to the address of the message; and
updating, by the L2 controller, a coherence state of the identified entry to be the coherence state of the message.

### Claim 2 (depends on 1)

The method of claim 1, further comprising receiving, by the L2 controller, a read or write request from the L1 controller over the transaction bus.

### Claim 3 (depends on 2)

The method of claim 2, wherein a transaction first-in, first-out buffer (FIFO) is coupled to the transaction bus, the method further comprising:
storing a transaction received from the L1 controller over the transaction bus in the transaction FIFO; and
not storing the message received from the L1 controller over the tag update bus in the transaction FIFO.

### Claim 4 (depends on 3)

The method of claim 3, further comprising processing, by the L2 controller, the message received from the L1 controller over the tag update bus upon receipt.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
receiving, by the L2 controller, parallel messages from the L1 controller over the tag update bus, each of the messages comprising a valid signal, an address, and a coherence state; and
for each one of the parallel messages, in response to the valid signal of the one of the messages being asserted:
identifying, by the L2 controller, an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the one of the messages; and
updating, by the L2 controller, a coherence state of the identified entry to be the coherence state of the one of the messages.

### Claim 6 (depends on 5)

The method of claim 5, wherein a number of parallel messages is 2.

### Claim 7 (depends on 1)

The method of claim 1, further comprising, in response to the valid signal being asserted, identifying, by the L2 controller, only an entry in the shadow L1 victim cache having an address corresponding to the address of the message.

### Claim 8

An apparatus, comprising:
a central processing unit (CPU) core;
a level one (L1) cache subsystem coupled to the CPU core, the L1 cache subsystem comprising:
a L1 main cache;
a L1 victim cache; and
a L1 controller;
a level two (L2) cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus, the L2 cache subsystem comprising:
a L2 main cache;
a shadow L1 main cache;
a shadow L1 victim cache; and
a L2 controller configured to:
receive a message from the L1 controller over the tag update bus, the message comprising a valid signal and an address; and
in response to the valid signal being asserted:
identify an entry in the shadow L1 victim cache having an address corresponding to the address of the message; and
update a coherence state of the identified entry to be invalid.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the L2 controller is further configured to receive a read or write request from the L1 controller over the transaction bus.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein:
the L2 cache subsystem further comprises a transaction first-in, first-out buffer (FIFO) coupled to the transaction bus;
a transaction received from the L1 controller over the transaction bus is stored in the transaction FIFO; and
the message received from the L1 controller over the tag update bus is not stored in the transaction FIFO.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the L2 controller is further configured to process the message received from the L1 controller over the tag update bus upon receipt.

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein the L2 controller is further configured to:
receive parallel messages from the L1 controller over the tag update bus, each of the messages comprising a valid signal and an address; and
for each one of the parallel messages, in response to the valid signal of the one of the messages being asserted:
identify an entry in the shadow L1 victim cache having an address corresponding to the address of the one of the messages; and
update a coherence state of the identified entry to be invalid.

### Claim 13 (depends on 8)

The apparatus of claim 8, wherein in response to the valid signal being asserted, the L2 controller is further configured to only identify an entry in the shadow L1 victim cache having an address corresponding to the address of the message.

### Claim 14

An apparatus, comprising:
a central processing unit (CPU) core;
a level one (L1) cache subsystem coupled to the CPU core, the L1 cache subsystem comprising:
a L1 main cache;
a L1 victim cache; and
a L1 controller;
a level two (L2) cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus, the L2 cache subsystem comprising:
a L2 main cache;
a shadow L1 main cache;
a shadow L1 victim cache; and
a L2 controller configured to:
receive a message from the L1 controller over the tag update bus, the message comprising a valid signal, an address, and a coherence state; and
in response to the valid signal being asserted:
identify an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message; and
update a coherence state of the identified entry to be the coherence state of the message.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the L2 controller is further configured to receive a read or write request from the L1 controller over the transaction bus.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein:
the L2 cache subsystem further comprises a transaction first-in, first-out buffer (FIFO) coupled to the transaction bus;
a transaction received from the L1 controller over the transaction bus is stored in the transaction FIFO; and
the message received from the L1 controller over the tag update bus is not stored in the transaction FIFO.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the L2 controller is further configured to process the message received from the L1 controller over the tag update bus upon receipt.

### Claim 18 (depends on 14)

The apparatus of claim 14, wherein the L2 controller is further configured to:
receive parallel messages from the L1 controller over the tag update bus, each of the messages comprising a valid signal, an address, and a coherence state; and
for each one of the parallel messages, in response to the valid signal of the one of the messages being asserted:
identify an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the one of the messages; and
update a coherence state of the identified entry to be the coherence state of the one of the messages.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein a number of parallel messages is 2.

### Claim 20 (depends on 14)

The apparatus of claim 14, wherein in response to the valid signal being asserted, the L2 controller is further configured to only identify an entry in the shadow L1 victim cache having an address corresponding to the address of the message.