# US 11,307,942 B2 · Memory system, memory controller and method for operating memory controller > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,942 B2 - Document ID: US11307942B2 - Status: Granted - Kind: B2 - Application number: 16/867,199 - Filed: 2020-05-05 - Published: 2021-05-06 - Granted: 2022-04-19 - Earliest claimed: 2019-10-31 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jin Pyo Kim - Web page: https://patentgrep.com/patent/US11307942B2 ## CPC - G06F 11/2015: {Redundant power supplies (power supply failure G06F1/30)} - G11C 5/005: {Circuit means for protection against loss of information of semiconductor storage devices} - G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) - G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit} - G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)} - G06F 11/3058: {Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206)} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G11C 16/26: Sensing or reading circuits; Data output circuits - G06F 11/3065: {Monitoring arrangements determined by the means or processing involved in reporting the monitored data (error or fault reporting or logging G06F11/0766)} - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks - G06F 2212/7204: Capacity control, e.g. partitioning, end-of-life degradation - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)} - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C 16/30: Power supply circuits - G11C 2029/0411: {Online error correction} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system, a memory controller and an operating method are disclosed. By dividing a read count table including read count values respectively for a plurality of memory blocks into one or more read count table segments each including one or more read count values of a resolution, and managing one or more flags respectively corresponding to the read count table segments, and set the flag corresponding to the read count table segment in which at least one read count value is changed among the read count table segments, it is possible to minimize additional operational costs required to recover the read count table upon occurrence of an SPO. ## Claims ### Claim 1 A memory system comprising: a memory device including a plurality of memory blocks; and a memory controller configured to: divide a read count table including read count values respectively for the plurality of memory blocks into one or more read count table segments each including one or more read count values of a resolution, manage one or more flags respectively corresponding to the read count table segments, and set the flag corresponding to the read count table segment, in which at least one read count value is changed, among the read count table segments. ### Claim 2 (depends on 1) The memory system according to claim 1, further comprising a power supply device configured to supply emergency power to the memory controller when a sudden power off (SPO) occurs, wherein the memory controller is further configured to determine a number of the read count values to be included in each of the read count table segments based on charge capacity of the power supply device. ### Claim 3 (depends on 1) The memory system according to claim 1, wherein the memory device further includes a first area, and wherein the memory controller is further configured to record, when a number of the set flags is equal to or greater than a threshold, the read count table segments corresponding to the set flags in the first area. ### Claim 4 (depends on 3) The memory system according to claim 3, wherein the first area is configured to store meta information on user data stored in the memory device. ### Claim 5 (depends on 3) The memory system according to claim 3, wherein the memory controller is further configured to reset the set flag corresponding to the read count table segment which is recorded in the first area. ### Claim 6 (depends on 3) The memory system according to claim 3, wherein the memory controller is further configured to determine a priority for recording the read count table segments corresponding to the set flags in the first area based on a number of changed read count values within each of the read count table segments corresponding to the set flags. ### Claim 7 (depends on 1) The memory system according to claim 1, wherein the memory device further includes a second area, and wherein the memory controller is further configured to record, when an SPO occurs, the read count table segments corresponding to set flags in the second area. ### Claim 8 (depends on 7) The memory system according to claim 7, wherein the memory controller is further configured to update, in an SPO recovery operation, the read count table based on the read count table segments recorded in the second area. ### Claim 9 A memory controller comprising: a memory interface configured to communicate with a memory device including a plurality of memory blocks; and a control circuit configured to: divide a read count table including read count values respectively for the plurality of memory blocks into one or more read count table segments each including one or more read count values of a resolution, manage one or more flags respectively corresponding to the read count table segments, and set the flag corresponding to the read count table segment, in which at least one read count value is changed, among the read count table segments. ### Claim 10 (depends on 9) The memory controller according to claim 9, wherein the control circuit is further configured to determine a number of the read count values to be included in each of the read count table segments based on charge capacity of a power supply device which supplies emergency power to the memory controller when an sudden power off (SPO) occurs. ### Claim 11 (depends on 9) The memory controller according to claim 9, wherein the control circuit is further configured to record, when a number of the set flags is equal to or greater than a threshold, the read count table segments corresponding to the set flags in a first area in the memory device. ### Claim 12 (depends on 11) The memory controller according to claim 11, wherein the first area is an area in which meta information on user data stored in the memory device is stored. ### Claim 13 (depends on 11) The memory controller according to claim 11, wherein the control circuit is further configured to reset the set flag corresponding to the read count table segment which is recorded in the first area. ### Claim 14 (depends on 11) The memory controller according to claim 11, wherein the control circuit is further configured to determine a priority for recording the read count table segments corresponding to the set flags in the first area based on a number of changed read count values within each of the read count table segments corresponding to the set flags. ### Claim 15 (depends on 9) The memory controller according to claim 9, wherein the control circuit is further configured to record, when an SPO occurs, the read count table segments corresponding to set flags in a second area in the memory device. ### Claim 16 (depends on 15) The memory controller according to claim 15, wherein the control circuit is further configured to update, in an SPO recovery operation, the read count table based on the read count table segments recorded in the second area. ### Claim 17 A method for operating a memory controller which controls a memory device including a plurality of memory blocks, the method comprising: dividing a read count table including read count values respectively for the plurality of memory blocks into one or more read count table segments each including one or more read count values of a resolution; managing one or more flags respectively corresponding to the read count table segments; and setting the flag corresponding to the read count table segment, in which at least one read count value is changed, among the read count table segments.