# US 11,307,928 B2 · Multichip package link error detection

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- Number: US 11,307,928 B2
- Document ID: US11307928B2
- Status: Granted
- Kind: B2
- Application number: 16/938,842
- Filed: 2020-07-24
- Published: 2020-11-12
- Granted: 2022-04-19
- Earliest claimed: 2020-01-31
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Venkatraman Iyer; Robert G. Blankenship; Mahesh Wagh; Zuoguo Wu
- Web page: https://patentgrep.com/patent/US11307928B2

## CPC

- H04L 1/0041: {Arrangements at the transmitter end}
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- H04L 1/00: Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)}
- H04L 1/0045: {Arrangements at the receiver end}
- H04L 1/0061: {Error detection codes}
- H04L 1/0075: {Transmission of coding parameters to receiver (H04L1/0023 takes precedence)}
- H04L 1/20: using signal quality detector
- H04L 9/40: Network security protocols
- G06F 2213/16: Memory access
- H04L 1/1607: Details of the supervisory signal
- H04L 2001/0094: {Bus}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

## Claims

### Claim 1

An apparatus comprising:
a physical layer interface to implement a physical layer of a link, wherein the link is to couple the interface to another device and the physical layer interface comprises:
a clock lane conductor to couple to a clock lane to support a clock signal;
a set of conductors to implement a control interface to support one or more control signals, wherein the one or more control signals comprise control signals to cause transitions in link states according to a state machine;
a plurality of data lane conductors to couple to a plurality of data lanes to transmit a packet, wherein the packet is to be transmitted as a set of flits on the plurality of data lanes, and the packet is to comprise a cyclic redundancy check (CRC) value associated with the packet; and
a valid signal conductor to couple to a valid signal lane to transmit a valid signal, wherein transmission of data on the data lanes is to be aligned with transmission of the valid signal on the valid signal lane.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the CRC value comprises at least 13 bits.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the link comprises at least the plurality of data lanes and the valid signal lane.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the protocol circuitry is to train the link, wherein the link is to comprise the plurality of data lanes.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the protocol circuitry is to use a state machine in training of the link.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the control signals comprise out-of-band control signals.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the physical layer interface comprises a logical PHY.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein a start of the valid signal is to be aligned with start of transmission of data on the plurality of data lanes.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the valid signal is aligned with an edge in the clock signal.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the link states comprises an active link state, a low-power link state, and a down link state.

### Claim 11

A method comprising:
receiving a clock signal on a dedicated clock lane of a link at a first device, wherein the link couples the first device to a second device;
receiving a control signal on a control lane of the link, wherein the control signal is to cause transitions in link states according to a state machine;
receiving a valid signal on a dedicated valid lane of the link;
determining that data received on a plurality of data lanes of the link is valid based on the valid signal;
receiving at least a portion of a packet on the plurality of data lanes, wherein the valid signal corresponds to the portion of the packet, the portion of the packet is received as a set of flits, and the portion of the packet comprises a cyclic redundancy check (CRC) value for the packet; and
determining whether errors are present in the packet based on the CRC value.

### Claim 12 (depends on 11)

The method of claim 11, wherein the valid signal is to align with a beginning of receipt of the portion of the packet.

### Claim 13 (depends on 11)

The method of claim 11, wherein the CRC comprises at least 13 bits.

### Claim 14

A system comprising:
a first computing device;
a second computing device connected to the first computing device by a link, wherein the second computing device comprises:
protocol circuitry to train the link; and
a physical layer interface comprising:
a clock lane conductor to couple to a clock lane to support a clock signal;
a set of conductors to implement a control interface to support one or more control signals, wherein the one or more control signals comprise control signals to cause transitions in link states according to a state machine;
a plurality of data lane conductors to couple to a plurality of data lanes to transmit a packet of data, wherein the packet is to be transmitted as a set of flits, and the packet is to comprise a cyclic redundancy check (CRC) value associated with the packet; and
a valid signal conductor to couple to a valid signal lane to transmit a valid signal, wherein transmission of data on the data lanes is to be aligned with transmission of the valid signal on the valid signal lane.

### Claim 15 (depends on 14)

The system of claim 14, wherein the valid signal is to align with a beginning of receipt of the portion of the packet, and the CRC comprises at least 13 bits.

### Claim 16 (depends on 14)

The system of claim 14, wherein the second computing device comprises a processor.

### Claim 17 (depends on 15)

The system of claim 15, wherein the processor comprises a second processor, and the first computing device comprises a first processor.

### Claim 18 (depends on 14)

The system of claim 14, wherein the second computing device comprises a memory controller.

### Claim 19 (depends on 14)

The system of claim 14, wherein the second computing device comprises a graphics processor.

### Claim 20 (depends on 14)

The system of claim 14, wherein the second computing device comprises a network controller.