# US 11,307,926 B2 · Memory system, operation method of the same, and memory controller

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- Number: US 11,307,926 B2
- Document ID: US11307926B2
- Status: Granted
- Kind: B2
- Application number: 16/570,504
- Filed: 2019-09-13
- Published: 2020-06-25
- Granted: 2022-04-19
- Earliest claimed: 2018-12-20
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Tae-Pyeong Kim; Jae-Woo Kim; Hyun-Jin Noh; Pyo-Young Han
- Web page: https://patentgrep.com/patent/US11307926B2

## CPC

- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G11C 7/1093: {Input synchronization}
- G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 2207/2254: Calibration
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for operating a memory system includes: performing a first training operation for alignment between a clock and a data strobe signal; performing a second training operation for alignment between the data strobe signal and the data; detecting an error of the second training operation; and adjusting a delay value of the data strobe signal in response to the detection of the error.

## Claims

### Claim 1

A method for operating a memory system, comprising:
performing a first training operation for alignment between a clock and a data strobe signal;
performing a second training operation for alignment between the data strobe signal and data;
detecting an error of the second training operation; and
adjusting a delay value of the data strobe signal for the first training operation in response to the detection of the error.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
performing the first training operation and the second training operation again, after the adjusting of the delay value of the data strobe signal.

### Claim 3 (depends on 2)

The method of claim 2, wherein the adjusting of the delay value of the data strobe signal includes
increasing or decreasing the delay value of the data strobe signal by one clock.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
re-detecting an error of the second training operation again after the first training operation and the second training operation are performed again; and
re-adjusting the delay value of the data strobe signal in response to the re-detecting the error for the first training operation,
wherein in the re-adjusting the delay value, the delay value is decreased when the delay value is increased in the adjusting the delay value, and the delay value is increased when the delay value is decreased in the adjusting the delay value.

### Claim 5 (depends on 1)

The method of claim 1, wherein the performing of the first training operation includes:
transferring, by a memory controller, the clock and the data strobe signal to a memory;
sampling, by the memory, the clock in synchronization with the data strobe signal to generate a sampling result and transferring the sampling result to the memory controller; and
adjusting, by the memory controller, the delay value of the data strobe signal based on the sampling result.

### Claim 6 (depends on 1)

The method of claim 1, wherein the performing of the second training operation includes:
transferring, by the memory controller, the data strobe signal and the data to the memory;
receiving, by the memory, the data based on the data strobe signal;
feeding back, by the memory, the received data to the memory controller; and
adjusting, by the memory controller, the delay value of the data based on the fed-back data.

### Claim 7

A memory controller, comprising:
a clock transfer circuit suitable for transferring a clock;
a data strobe signal transfer circuit suitable for transferring a data strobe signal;
a data strobe signal delay circuit suitable for delaying a preliminary data strobe signal by a first delay value to generate the data strobe signal;
a data receiving circuit;
a data transfer circuit suitable for transferring data;
a data delay circuit suitable for delaying a preliminary data by a second delay value to generate the data;
a first training control circuit suitable for adjusting the first delay value in response to a signal received by the data receiving circuit during a first training operation for alignment between the clock and the data strobe signal; and
a second training control circuit for adjusting the second delay value in response to a signal received by the data receiving circuit during a second training operation for alignment between the data strobe signal and the data,
wherein, when the second training control circuit detects an error of the second training operation, the second training control circuit adjusts the first delay value.

### Claim 8 (depends on 7)

The memory controller of claim 7, wherein the second training operation is performed after the first training operation is completed, and
wherein the first training operation and the second training operation are performed again, after the first delay value is adjusted in response to detecting an error of the second training operation.

### Claim 9 (depends on 8)

The memory controller of claim 8, wherein the first delay value is increased by one clock, when an error of the second training operation is detected.

### Claim 10 (depends on 8)

The memory controller of claim 8, wherein the first delay value is decreased by one clock, when an error of the second training operation is detected.

### Claim 11

A memory system, comprising:
a memory controller suitable for adjusting a first delay value for a data strobe signal in response to a sampling result for alignment between a clock and the data strobe signal during a first training operation, adjusting a second delay value for data in response to feedback data for alignment between the data strobe signal and the data during a second training operation which is performed after the first training operation, and when an error of the second training operation is detected, adjusting the first delay value and then performing the first training operation and the second training operation again; and
a memory suitable for sampling the clock received from the memory controller based on the data strobe signal received from the memory controller to produce a sampling result during the first training operation and transferring the sampling result to the memory controller, receiving the data from the memory controller based on the data strobe signal received from the memory controller during the second training operation, and transferring the received data to the memory controller as the feedback data.

### Claim 12 (depends on 11)

The memory system of claim 11, wherein the memory controller increases the first delay value by one clock, when an error of the second training operation is detected.

### Claim 13 (depends on 11)

The memory system of claim 11, wherein the memory controller decreases the first delay value by one clock, when an error of the second training operation is detected.