# US 11,307,919 B2 · Fail information control circuit, semiconductor apparatus including the same, and fail information control method of semiconductor apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,919 B2 - Document ID: US11307919B2 - Status: Granted - Kind: B2 - Application number: 16/709,273 - Filed: 2019-12-10 - Published: 2021-01-07 - Granted: 2022-04-19 - Earliest claimed: 2019-07-03 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jae Yong Kang - Web page: https://patentgrep.com/patent/US11307919B2 ## CPC - G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)} - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)} - G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A fail information control circuit may include: a comparison circuit configured to generate a comparison result signal by comparing read data and write data; a fail bit discrimination circuit configured to generate a first fail discrimination signal for discriminating a fail detected when the write data has a first value and a second fail discrimination signal for discriminating a fail detected when the write data has a second value, in response to the comparison result signal; and a fail bit counter configured to generate a first counting signal by counting the first fail discrimination signal and generate a second counting signal by counting the second fail discrimination signal. ## Claims ### Claim 1 A fail information control circuit comprising: a comparison circuit configured to generate a comparison result signal by comparing read data and write data; a fail bit discrimination circuit configured to: generate a first fail discrimination signal when a fail detected where the write data has a value ‘0’; and generate a second fail discrimination signal when a fail detected where the write data has a value ‘1’, in response to the comparison result signal; and a fail bit counter configured to generate a first counting signal by counting the first fail discrimination signal and generate a second counting signal by counting the second fail discrimination signal. ### Claim 2 (depends on 1) The fail information control circuit according to claim 1, further comprising: a counting signal correction circuit configured to: output, as a first counting correction signal, a signal obtained by resetting levels of remaining bits, except for a most significant bit among high level bits of the first counting signal, to a low level; and output, as a second counting correction signal, a signal obtained by resetting levels of remaining bits, except for a most significant bit among high level bits of the second counting signal, to a low level. ### Claim 3 (depends on 1) The fail information control circuit according to claim 1, wherein the fail bit discrimination circuit comprises: a first logic gate configured to invert the write data and output the inverted write data as an output signal; a second logic gate configured to output the second fail discrimination signal by performing a logical AND operation on the comparison result signal and the write data; and a third logic gate configured to output the first fail discrimination signal by performing a logical AND operation on the comparison result signal and the output signal of the first logic gate. ### Claim 4 A fail information control circuit comprising: a comparison circuit configured to generate a comparison result signal by comparing read data and write data; a fail bit discrimination circuit configured to generate a first fail discrimination signal for discriminating a fail detected when the write data has a first value and a second fail discrimination signal for discriminating a fail detected when the write data has a second value, in response to the comparison result signal; and a fail information output circuit configured to: generate a first counting signal and a second counting signal by counting the first fail discrimination signal and the second fail discrimination signal; and generate a first counting correction signal and a second counting correction signal by resetting remaining bits, except for a most significant bit of a first level among bits of the first counting signal and the second counting signal. ### Claim 5 (depends on 4) The fail information control circuit according to claim 4, wherein the fail bit discrimination circuit comprises: a first logic gate configured to invert the write data and output the inverted write data as an output signal; a second logic gate configured to output the second fail discrimination signal by performing a logical AND operation on the comparison result signal and the write data; and a third logic gate configured to output the first fail discrimination signal by performing a logical AND operation on the comparison result signal and the output signal of the first logic gate. ### Claim 6 (depends on 4) The fail information control circuit according to claim 4, wherein the fail information output circuit comprises: a fail bit counter configured to: generate a first counting signal by counting the first fail discrimination signal; and generate a second counting signal by counting the second fail discrimination signal; and a counting signal correction circuit configured to: output, as the first counting correction signal, a signal obtained by resetting levels of the remaining bits, except for the most significant bit among bits having a first level of the first counting signal, to a second level; and output, as the second counting correction signal, a signal obtained by resetting levels of the remaining bits, except for the most significant bit among bits having the first level of the second counting signal, to the second level. ### Claim 7 A semiconductor apparatus comprising: a memory area; input/output pads; and a fail information control circuit configured to: generate a first fail discrimination signal when a fail detected where the write data has a value ‘0’ and generate a second fail discrimination signal when a fail detected where the write data has a value ‘1’ according to a result of comparing the write data provided to the memory area with read data outputted from the memory area; and generate a first counting signal by counting the first fail discrimination signal and generate a second counting signal by counting the second fail discrimination signal, wherein the first counting signal and the second counting signal are outputted to an exterior through the input/output pads. ### Claim 8 (depends on 7) The semiconductor apparatus according to claim 7, wherein the semiconductor apparatus outputs the first counting signal through one of the input/output pads and outputs the second counting signal through another one of the input/output pads. ### Claim 9 (depends on 7) The semiconductor apparatus according to claim 7, wherein the fail information control circuit is configured to: generate a first counting correction signal by resetting levels of remaining bits, except for a most significant bit among high level bits of the first counting signal, to a low level; and generate a second counting correction signal by resetting levels of remaining bits, except for a most significant bit among high level bits of the second counting signal, to a low level. ### Claim 10 (depends on 9) The semiconductor apparatus according to claim 9, wherein the semiconductor apparatus puts the first counting correction signal into one of data of a burst length outputted through one of the input/output pads, and puts the second counting correction signal into one of data of a burst length outputted through another one of the input/output pads. ### Claim 11 (depends on 7) The semiconductor apparatus according to claim 7, further comprising: a repair circuit configured to: control an operation of programming a failed address corresponding to a failed cell of memory cells of the memory area into a one-time programmable (OTP) memory; and control an operation of accessing an address corresponding to a redundancy memory cell instead of the failed address when an address provided from an exterior coincides with the failed address during a normal operation. ### Claim 12 (depends on 7) The semiconductor apparatus according to claim 7, further comprising: an ECC circuit configured to perform a correction operation using an error correction code on input/output data of the semiconductor apparatus. ### Claim 13 A fail information control method of a semiconductor apparatus, the method comprising: a comparison step of comparing read data and write data; a counting step of classifying a type of fail bits into a first fail when the write data and the read data do not coincide with each other in the comparison step, and generating a first counting signal; a counting step of classifying a type of fail bits into a first fail and a second fail when the write data and the read data do not coincide with each other in the comparison step, and generating a first counting signal and a second counting signal; and an output step of outputting the first counting signal and the second counting signal to an exterior of the semiconductor apparatus, wherein the counting step comprises: determining whether the write data is ‘0’ when the write data and the read data do not coincide with each other; and increasing a value of the first counting signal when the write data is determined to be ‘0’ and increasing a value of the second counting signal when the write data is determined not to be ‘0’. ### Claim 14 (depends on 13) The fail information control method according to claim 13, wherein the output step comprises: outputting the first counting signal through one of input/output pads of the semiconductor apparatus; and outputting the second counting signal through another one of the input/output pads. ### Claim 15 (depends on 13) The fail information control method according to claim 13, wherein the output step comprises: putting the first counting signal into one of data of a burst length outputted through one of the input/output pads; and putting the second counting signal into one of data of a burst length outputted through another one of the input/output pads. ### Claim 16 (depends on 13) The fail information control method according to claim 13, wherein the output step comprises: generating a first counting correction signal by resetting levels of remaining bits, except for a most significant bit among high level bits of the first counting signal, to a low level and outputting the first counting correction signal through one of the input/output pads of the semiconductor apparatus; and generating a second counting correction signal by resetting levels of remaining bits, except for a most significant bit among high level bits of the second counting signal, to a low level and outputting the second counting correction signal through another one of the input/output pads. ### Claim 17 (depends on 13) The fail information control method according to claim 13, wherein the output step comprises: generating a first counting correction signal by resetting levels of remaining bits, except for a most significant bit among high level bits of the first counting signal, to a low level and putting the first counting correction signal into one of data of a burst length outputted through one of the input/output pads; and generating a second counting correction signal by resetting levels of remaining bits, except for a most significant bit among high level bits of the second counting signal, to a low level and putting the second counting correction signal into one of data of a burst length outputted through another one of the input/output pads.