# US 11,307,918 B2 · Memory controller performing recovery operation, operating method of the same, and memory system including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,918 B2 - Document ID: US11307918B2 - Status: Granted - Kind: B2 - Application number: 16/594,400 - Filed: 2019-10-07 - Published: 2020-05-21 - Granted: 2022-04-19 - Earliest claimed: 2018-11-16 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Eun chu Oh; Young-Sik Kim; Hee-hyun Nam; Young-geun Lee; Young-jin Cho - Web page: https://patentgrep.com/patent/US11307918B2 ## CPC - G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit} - G06F 11/1489: using recovery blocks - G06F 11/3466: {Performance evaluation by tracing or monitoring} - G06F 13/1668: {Details of memory controller} - G11C 11/1659: {Cell access} - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/1675: {Writing or programming circuits or methods} - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 11/409: Read-write [R-W] circuits - G11C 11/5607: {using magnetic storage elements} - G11C 11/5678: {using amorphous/crystalline phase transition storage elements} - G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 13/003: {Cell access} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G06F 2201/88: Monitoring involving counting - G11C 2029/0411: {Online error correction} - G11C 2213/72: Array wherein the access device being a diode - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells. ## Claims ### Claim 1 A memory system comprising: a memory device comprising a plurality of memory cells constituting a plurality of sub-sets; and a memory controller configured to: manage, for each of the plurality of sub-sets, a read count indicating a number of read operations performed by the memory device for the respective sub-set among the plurality of sub-sets, identify a sub-set, among the plurality of sub-sets, which has the read count satisfying a criteria, and perform a recovery operation on the identified sub-set, wherein each of the plurality of sub-sets comprises a plurality of pages, and wherein each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells, wherein the memory device is configured to provide a recovery pulse to the sub-set corresponding to the read count when the read count reaches a first reference value. ### Claim 2 (depends on 1) The memory system of claim 1, wherein memory cells, among the plurality of memory cells, connected to a same word line are included in a same sub-set. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the memory controller is further configured to manage a write count for a number of write operations performed by the memory device in each of the plurality of sub-sets. ### Claim 4 (depends on 1) The memory system of claim 1, wherein the recovery pulse has a different voltage level than a voltage level of a pulse for writing operation. ### Claim 5 (depends on 1) The memory system of claim 1, wherein the recovery pulse has a different pulse duration than a pulse duration of a pulse for writing operation. ### Claim 6 (depends on 1) The memory system of claim 1, wherein when the read count reaches a second reference value, the memory device is configured to read out data written in the sub-set corresponding to the read count and transmit the read data to the memory controller. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the memory controller is further configured to receive data read from the sub-set, correct an error in the received data, and transmit error correction data to the memory device. ### Claim 8 (depends on 7) The memory system of claim 7, wherein the memory device is configured to write the error correction data to the sub-set corresponding to the read count. ### Claim 9 (depends on 8) The memory system of claim 8, wherein the memory device is further configured to rewrite the error correction data in the memory cell even when the read data and the error correction data are the same. ### Claim 10 (depends on 8) The memory system of claim 8, wherein the memory device is further configured to perform a data compare-write operation on the sub-set corresponding to the read count. ### Claim 11 A method of operating a memory controller for controlling an operation of a memory device comprising a plurality of memory cells constituting a plurality of sub-sets, the method comprising: transmitting a read command to the memory device; increasing a read count for a sub-set, among the plurality of sub-sets, corresponding to the read command; determining whether the read count of the sub-set satisfies a criteria; and performing a recovery operation on the sub-set based on a result of the determination that the read count of the sub-set satisfies the criteria, wherein the sub-set comprises a plurality of pages, and wherein each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells, wherein the performing of the recovery operation comprises: determining whether the read count reaches a second reference value; transmitting a read command for the sub-set corresponding to the read count based on a determination that the read count reaches the second reference value; correcting an error in data read from the sub-set; and transmitting a rewrite command for the sub-set and the corrected data to the memory device to allow the corrected data to be rewritten to the sub-set. ### Claim 12 (depends on 11) The method of claim 11, wherein the performing of the recovery operation comprises: determining whether the read count reaches a first reference value; and transmitting a recovery command to the memory device based on a determination that the read count reaches the first reference value. ### Claim 13 (depends on 11) The method of claim 11, further comprising resetting the read count after the performing of the recovery operation is completed. ### Claim 14 (depends on 11) The method of claim 11, further comprising confirming whether a request for the sub-set is received from a host, wherein the recovery operation is performed when the request for the sub-set is not received. ### Claim 15 (depends on 11) The method of claim 11, further comprising confirming whether a read request for the sub-set is received from a host, wherein, when the read request for the sub-set is received, an operation according to the read request is performed after the recovery operation is performed. ### Claim 16 (depends on 11) The method of claim 11, further comprising confirming whether a request for the sub-set is received from a host, wherein, when the request for the sub-set other than a read request is received, the recovery operation is performed after an operation according to the request is performed. ### Claim 17 A memory controller for controlling a memory device comprising a plurality of memory cells constituting a plurality of sub-sets, the memory controller comprising: a memory configured to store one or more instruction; and at least one processor configured to execute the one or more instructions to: manage, for each of the plurality of sub-sets, a read count, which indicates a number of read commands transmitted to the memory device for the respective sub-set among the plurality of sub-sets, identify a sub-set, among the plurality of sub-sets, which has the read count satisfying a criteria, output an instruction to perform a recovery operation the identified sub-set, wherein each of the plurality of sub-sets comprises a plurality of pages, and wherein each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells, wherein the at least one processor is further configured to: transmit a recovery command to the memory device such that a recovery pulse is provided to the sub-set corresponding to the read count, based on a result of the determination that the read count reaches a first reference value, and transmit a rewrite command such that data is rewritten in the sub-set, when the read count reaches a second reference value, and wherein the first reference value is less than the second reference value, and wherein memory cells connected to the same word line among the plurality of memory cells are included in the same sub-set.