# US 11,307,858 B2 · Cache preload operations using streaming engine

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- Number: US 11,307,858 B2
- Document ID: US11307858B2
- Status: Granted
- Kind: B2
- Application number: 16/827,875
- Filed: 2020-03-24
- Published: 2020-09-10
- Granted: 2022-04-19
- Earliest claimed: 2013-07-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Joseph Raymond Michael Zbiciak; Timothy David Anderson; Jonathan (Son) Hung Tran; Kai Chirca; Daniel Wu; Abhijeet Ashok Chachad; David M. Thompson
- Web page: https://patentgrep.com/patent/US11307858B2

## CPC

- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 9/30014: {with variable precision}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/30098: {Register arrangements}
- G06F 9/30112: {comprising data of variable length}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/32: Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence)
- G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)}
- G06F 9/3802: {Instruction prefetching}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F 9/3867: {using instruction pipelines}
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 12/0862: with prefetch
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence)
- G06F 9/3822: {Parallel decoding, e.g. parallel decode units}
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 2212/1024: Latency reduction
- G06F 2212/452: Instruction code
- G06F 2212/60: Details of cache memory
- G06F 2212/6022: Using a prefetch buffer or dedicated prefetch cache
- G06F 2212/6028: Prefetching based on hints or prefetch instructions
- G06F 2212/657: Virtual address space management
- G06F 2212/681: Multi-level TLB, e.g. microTLB and main TLB
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

## Claims

### Claim 1

A method comprising:
receiving an instruction that specifies:
a set of data based on a base address and a data size;
a level of a cache memory to be preloaded with the set of data; and
whether to preload the level of the cache memory with the set of data for a subsequent read or a subsequent write to a set of addresses of the set of data, wherein the subsequent read or the subsequent write occurs after the cache memory has been preloaded with the set of data;
determining, based on the base address and the data size, the set of addresses of the set of data; and
issuing a set of cache preload operations to the cache memory that includes a cache preload operation for each address in the set of addresses.

### Claim 2 (depends on 1)

The method of claim 1, wherein the cache memory includes a level 2 (L2) cache and a level 3 (L3) cache, and the instruction specifies whether to operate on the L2 cache or the L3 cache.

### Claim 3 (depends on 1)

The method of claim 1, wherein the cache memory includes a level 1 (L1) cache and a level 2 (L2) cache, and the set of cache preload operations are issued to the L2 cache via a data path that does not include the L1 cache.

### Claim 4 (depends on 1)

The method of claim 1 further comprising, when the instruction specifies to preload the level of the cache memory for the subsequent read, the set of cache preload operations request to preload the cache memory in a shared access mode.

### Claim 5 (depends on 1)

The method of claim 1 further comprising, when the instruction specifies to preload the level of the cache memory for the subsequent write, the set of cache preload operations request to preload the cache memory in an exclusive access mode.

### Claim 6 (depends on 1)

The method of claim 1, wherein the instruction is a first instruction, the method further comprising:
asserting an indicator of the set of cache preload operations during the issuing of the set of cache preload operations to the cache memory; and
in response to the indicator, causing a processor wait to execute a second instruction.

### Claim 7 (depends on 1)

The method of claim 1, wherein:
the set of addresses includes a virtual address;
the method further comprises translating the virtual address to a physical address; and
the issuing of a cache preload operation associated with the virtual address uses the physical address.

### Claim 8 (depends on 1)

The method of claim 1 further comprising:
determining that an address of the set of addresses is invalid; and
notifying a processor that the address is invalid.

### Claim 9 (depends on 1)

The method of claim 1 further comprising:
determining that an address of the set of addresses causes a page fault; and
notifying a processor of the page fault.

### Claim 10 (depends on 9)

The method of claim 9 further comprising:
saving a state of the set of cache preload operations prior to the page fault;
moving a new page of data into the cache memory; and
resuming the set of cache preload operations using the saved state.

### Claim 11

A method comprising:
receiving an instruction that specifies a base address, a data size, and a level of a cache memory to operate on;
determining, based on the base address and the data size, a set of addresses associated with the instruction; and
issuing a set of cache preload operations to the cache memory that includes a cache preload operation for each address in the set of addresses, wherein:
the instruction has an associated privilege level; and
the method further comprises:
for each cache preload operation in the set of cache preload operations, determining whether the privilege level permits preload of the respective address of the cache preload operation; and
when the privilege level does not permit preload of a first cache preload operation of the set of cache preload operations, dropping the first cache preload operation while proceeding with a remainder of the set of cache preload operations.

### Claim 12

A method comprising:
receiving an instruction that specifies a base address, a data size, and a level of a cache memory to operate on;
determining, based on the base address and the data size, a set of addresses associated with the instruction;
issuing a set of cache preload operations to the cache memory that includes a cache preload operation for each address in the set of addresses;
determining whether each cache preload operation of the set of cache preload operations is directed to cacheable memory; and
when a first cache preload operation of the set of cache preload operations is directed to non-cacheable memory, dropping the first cache preload operation while proceeding with a remainder of the set of cache preload operations.

### Claim 13

A system comprising:
a processor;
a memory coupled to the processor that includes a cache memory; and
a memory component coupled to the processor and the memory, wherein the memory component is operable to:
receive an instruction from the processor that specifies:
a set of data;
a level of the cache memory to preload with the set of data; and
whether to preload the level of the cache memory with the set of data for a subsequent read or a subsequent write to a set of addresses of the set of data, wherein the subsequent read or the subsequent write occurs after the cache memory has been preloaded with the set of data;
determine the set of addresses based on the instruction; and
issue a set of cache preload operations to the cache memory that includes a cache preload operation for each address in the set of addresses.

### Claim 14 (depends on 13)

The system of claim 13, wherein:
the instruction further specifies a base address and an amount of data; and
the memory component is operable to determine the set of addresses based on the base address and the amount of data.

### Claim 15 (depends on 13)

The system of claim 13, wherein the cache memory includes a level 2 (L2) cache and a level 3 (L3) cache, and the instruction specifies whether to operate on the L2 cache or the L3 cache.

### Claim 16 (depends on 15)

The system of claim 15, wherein the memory component is coupled to the L2 cache and is operable to issue the set of cache preload operations directly to the L2 cache.

### Claim 17 (depends on 13)

The system of claim 13, wherein the memory component is operable to:
when the instruction specifies to preload the level of the cache memory for the subsequent read, issue the set of cache preload operations to preload the cache memory in a shared access mode; and
when the instruction specifies to preload the level of the cache memory for the subsequent write, issue the set of cache preload operations to preload the cache memory in an exclusive access mode.

### Claim 18 (depends on 13)

The system of claim 13, wherein the memory component is operable to:
determine whether each cache preload operation of the set of cache preload operations is directed to cacheable memory; and
when a first cache preload operation of the set of cache preload operations is directed to non-cacheable memory, drop the first cache preload operation while proceeding with a remainder of the set of cache preload operations.

### Claim 19 (depends on 13)

The system of claim 13, wherein the memory component is further operable to:
detect that a first address of the set of addresses is associated with a page fault;
in response to the page fault, save a current state of the set of cache preload operations; and
resume the set of cache preload operations using the current state after the page fault is resolved.

### Claim 20 (depends on 19)

The system of claim 19, wherein the memory component is further operable to, in response to the page fault, notifying the processor of the page fault.