# US 11,307,857 B2 · Dynamic designation of instructions as sensitive for constraining multithreaded execution

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,307,857 B2
- Document ID: US11307857B2
- Status: Granted
- Kind: B2
- Application number: 17/081,099
- Filed: 2020-10-27
- Published: 2021-06-10
- Granted: 2022-04-19
- Earliest claimed: 2019-12-05
- Assignees: Marvell Asia Pte Ltd
- Applicants: Marvell Asia Pte, Ltd.
- Inventors: Shubhendu Sekhar Mukherjee
- Web page: https://patentgrep.com/patent/US11307857B2

## CPC

- G06F 9/30156: {Special purpose encoding of instructions, e.g. Gray coding}
- G06F 9/30189: {according to execution mode, e.g. mode flag}
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/3009: {Thread control instructions}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30152: {Determining start or end of instruction; determining instruction length}
- G06F 9/38: Concurrent instruction execution, e.g. pipeline or look ahead
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating}
- G06F 9/3867: {using instruction pipelines}
- G06F 9/45533: {Hypervisors; Virtual machine monitors}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 21/556: {involving covert channels, i.e. data leakage between processes (inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755)}
- G06F 9/455: Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F 2209/484: Precedence
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Described herein are systems and methods for dynamic designation of instructions as sensitive. For example, some methods include detecting that a first instruction of a first process has been designated as a sensitive instruction; checking whether a sensitive handling enable indicator in a process state register storing a state of the first process is enabled; responsive to detection of the sensitive instruction and enablement of the sensitive handling enable indicator, invoking a constraint for execution of the first instruction; executing the first instruction subject to the constraint; and executing a second instruction of the first process without the constraint.

## Claims

### Claim 1

An integrated circuit for executing instructions, comprising:
a register that includes a sensitive handling enable indicator; and
a processor core configured to:
detect that a first instruction of a first process has been designated as a sensitive instruction by evaluating a sensitive bit included in the first instruction;
check whether the sensitive handling enable indicator is enabled;
responsive to detection of the sensitive instruction and enablement of the sensitive handling enable indicator, invoke a constraint for execution of the first instruction;
execute the first instruction subject to the constraint; and
execute a second instruction of the first process without the constraint.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, in which the first instruction is preceded by a sensitive-start instruction and followed by a sensitive-stop instruction in a sequence of instructions of the first process, and the processor core is configured to detect that the first instruction has been designated as a sensitive instruction based on detection of the sensitive-start instruction.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, in which the first instruction is a member of a subsequence of instructions that is immediately preceded by the sensitive-start instruction and immediately followed by the sensitive-stop instruction in the sequence of instructions of the first process, and the processor core is configured to execute all members of the subsequence of instructions subject to the constraint.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, in which the processor core is configured to update a value of the sensitive handling enable indicator based on an instruction of a second process that has a higher priority than the first process.

### Claim 5 (depends on 4)

The integrated circuit of claim 4, in which the second process is a hypervisor process.

### Claim 6 (depends on 4)

The integrated circuit of claim 4, in which the second process is an operating system process.

### Claim 7 (depends on 4)

The integrated circuit of claim 4, in which the processor core is configured to:
detect that a third instruction of a third process has been designated as a sensitive instruction;
check whether the sensitive handling enable indicator is enabled; and
responsive to disablement of the sensitive handling enable indicator, execute the third instruction of the third process without the constraint.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, comprising:
a processor pipeline configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline; and
in which the constraint prevents parallel execution of instructions from other threads while the first instruction is being executed by an execution unit of the processor pipeline.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, in which the register is a process state register storing a state of the first process.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, in which the first instruction is a cryptographic instruction.

### Claim 11 (depends on 1)

The integrated circuit of claim 1, in which the sensitive handling enable indicator consists of a single bit.

### Claim 12

A method comprising:
detecting that a first instruction of a first process has been designated as a sensitive instruction, where the detecting comprises evaluating a sensitive bit included in the first instruction;
checking whether a sensitive handling enable indicator in a process state register storing a state of the first process is enabled;
responsive to detection of the sensitive instruction and enablement of the sensitive handling enable indicator, invoking a constraint for execution of the first instruction;
executing the first instruction subject to the constraint; and
executing a second instruction of the first process without the constraint.

### Claim 13 (depends on 12)

The method of claim 12, in which the first instruction is preceded by a sensitive-start instruction and followed by a sensitive-stop instruction in a sequence of instructions of the first process, and the method comprises:
detecting that the first instruction has been designated as a sensitive instruction based on detection of the sensitive-start instruction.

### Claim 14 (depends on 13)

The method of claim 13, in which the first instruction is a member of a subsequence of instructions that is immediately preceded by the sensitive-start instruction and immediately followed by the sensitive-stop instruction in the sequence of instructions of the first process, and the method comprises:
executing all members of the subsequence of instructions subject to the constraint.

### Claim 15 (depends on 12)

The method of claim 12, comprising:
updating a value of the sensitive handling enable indicator based on an instruction of a second process that has a higher priority than the first process.

### Claim 16 (depends on 15)

The method of claim 15, in which the second process is a hypervisor process.

### Claim 17 (depends on 15)

The method of claim 15, in which the second process is an operating system process.

### Claim 18 (depends on 15)

The method of claim 15, comprising:
detecting that a third instruction of a third process has been designated as a sensitive instruction;
checking whether a sensitive handling enable indicator associated with the third process is enabled; and
responsive to disablement of the sensitive handling enable indicator associated with the third process, executing the third instruction of the third process without the constraint.

### Claim 19 (depends on 12)

The method of claim 12, in which the constraint prevents parallel execution of instructions from other threads while the first instruction is being executed by an execution unit of a processor pipeline, wherein the processor pipeline is configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline.

### Claim 20 (depends on 12)

The method of claim 12, in which the first instruction is a cryptographic instruction.

### Claim 21 (depends on 12)

The method of claim 12, in which the sensitive handling enable indicator consists of a single bit.