# US 11,307,854 B2 · Memory write log storage processors, methods, systems, and instructions

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,307,854 B2
- Document ID: US11307854B2
- Status: Granted
- Kind: B2
- Application number: 15/891,028
- Filed: 2018-02-07
- Published: 2019-08-08
- Granted: 2022-04-19
- Earliest claimed: 2018-02-07
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kshitij Doshi; Roman Dementiev; Vadim Sukhomlinov
- Web page: https://patentgrep.com/patent/US11307854B2

## CPC

- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/3004: {to perform operations on memory}
- G06F 9/3834: {Maintaining memory consistency}
- G06F 11/30: Monitoring
- G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/30178: {of compressed or encrypted instructions}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 2212/452: Instruction code
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a destination memory address information. An execution unit is coupled with the decode unit. The execution unit, in response to the decode of the instruction, is to store memory addresses, for at least all initial writes to corresponding data items, which are to occur after the instruction in original program order, to a memory address log. A start of the memory address log is to correspond to the destination memory address information. Other processors, methods, systems, and instructions are also disclosed.

## Claims

### Claim 1

A processor comprising:
a decode unit to decode an instruction, the instruction to indicate a destination memory address information corresponding to a start of a memory address log; and
an execution unit coupled with the decode unit, the execution unit to perform the instruction, to:
begin to log memory addresses to the memory address log, including to store memory addresses, for at least all initial writes to corresponding initial data items, to the memory address log, wherein the initial writes represent first writes to the initial data items that occur after the instruction in original program order to update the corresponding initial data items to updated data items; and
store the initial data items, for said at least all initial writes, to a data item log, wherein the initial data items do not reflect the updates due to said at least all initial writes.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the execution unit, in response to the decode of the instruction, is to said store the memory addresses in a same order in position in the memory address log as an order that the associated said at least all initial writes occur over time.

### Claim 3 (depends on 2)

The processor of claim 2, wherein the execution unit, in response to the decode of the instruction, is to said store the memory addresses in consecutive positions in the memory address log.

### Claim 4 (depends on 3)

The processor of claim 3, wherein the execution unit, in response to the decode of the instruction, is to update a value, which is to be indicative of a memory location in the memory address log where a next memory address is to be stored, to account for a size of a memory address, when each of the memory addresses is said stored to the memory address log.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the decode unit is to decode the instruction that is to have at least one field indicate a second destination memory address information, and wherein the execution unit, in response to the decode of the instruction, is to said store the initial data items to the data item log, wherein a start of the data item log is to correspond to the second destination memory address information.

### Claim 6 (depends on 1)

The processor of claim 1, wherein the data item log is a combined memory address and data item log, and wherein the corresponding memory addresses and the initial data items are to be interleaved with one another in the combined memory address and data item log.

### Claim 7 (depends on 1)

The processor of claim 1, wherein the execution unit, in response to the decode of the instruction, is to store times indicative of when said at least all initial writes are performed to a time log.

### Claim 8 (depends on 1)

The processor of claim 1, wherein the execution unit, in response to the decode of the instruction, is to stop storing the memory addresses to the memory address log when an end memory write log condition occurs.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the execution unit, in response to the decode of the instruction, is to:
detect the occurrence of the end memory write log condition as a lack of resources to further track said at least all initial writes; and
store an indication in an architecturally-visible storage location that the lack of resources was detected.

### Claim 10 (depends on 1)

The processor of claim 1, wherein the decode unit is also to decode a second instruction that is to indicate a destination storage location, and further comprising a second execution unit coupled with the decode unit, the second execution unit, in response to the decode of the second instruction, to:
cause the processor to stop storing memory addresses to the memory address log due to performance of the instruction; and
store information indicative of a last memory location in the memory address log that was stored to, during the performance of the instruction, to the indicated destination storage location.

### Claim 11 (depends on 10)

The processor of claim 10, wherein the information indicative of the last memory location is either a memory pointer to point to the last memory location or an offset from the destination memory location indicated by the instruction.

### Claim 12 (depends on 10)

The processor of claim 10, wherein the second execution unit, in response to the decode of the second instruction, is to store an indication in an architecturally-visible storage location that the storage of the memory addresses to the memory address log was stopped due to the second instruction.

### Claim 13 (depends on 1)

The processor of claim 1, wherein the processor is to transform the memory addresses, prior to the storage of the memory addresses to the memory address log, through at least one of encryption, compression, and addition of redundancy data for the memory addresses.

### Claim 14 (depends on 1)

The processor of claim 1, wherein the data items are cache lines.

### Claim 15 (depends on 1)

The processor of claim 1, wherein the execution unit, in response to the decode of the instruction, is not to store memory addresses for subsequent writes to the data items, which occur after the initial writes to the data items, to the memory address log.

### Claim 16 (depends on 1)

The processor of claim 1, wherein the execution unit comprises transactional execution write-set tracking logic to track data items written to while performing the instruction.

### Claim 17 (depends on 1)

The processor of claim 1, wherein the execution unit, in response to the decode of the instruction, is to log identifiers of processes that performed the initial writes.

### Claim 18

A method performed by a processor comprising:
receiving an instruction at the processor, the instruction indicating a destination memory address information corresponding to a start of a memory address log;
beginning to log memory addresses to the memory address log, in response to the instruction, including storing memory addresses, for at least all initial writes to corresponding initial data items, to the memory address log, wherein the initial writes represent first writes to the initial data items occurring after the instruction in original program order and updating the corresponding initial data items to updated data items; and
storing the initial data items, for said at least all initial writes, to a data item log, wherein the initial data items stored do not include the updates due to said at least all initial writes.

### Claim 19 (depends on 18)

The method of claim 18, further comprising, in response to the instruction storing times, which indicate when said at least all initial writes are performed, to a time log.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
receiving a second instruction at the processor, the second instruction indicating a destination storage location; and
in response to the second instruction:
causing the processor to stop storing memory addresses to the memory address log due to performance of the instruction; and
storing information indicative of a last memory location in the memory address log that was stored to, during the performance of the instruction, in the indicated destination storage location.

### Claim 21

A system to process instructions comprising:
an interconnect;
a processor coupled with the interconnect, the processor to receive an instruction, the instruction to indicate a destination memory address information corresponding to a start of a memory address log, the processor, in response to the instruction, to begin to log memory addresses to the memory address log, including to store memory addresses, for only all initial writes to corresponding data items, to the memory address log, wherein said initial writes represent first writes in time to the corresponding data items that occur after the instruction in original program order; and
a dynamic random-access memory (DRAM) coupled with the interconnect.

### Claim 22 (depends on 21)

The system of claim 21, wherein the processor, in response to the instruction, is to store the data items, for said only all initial writes, before the data items are updated due to said at least all initial writes, to a data item log.

### Claim 23

An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing a plurality of instructions including an instruction that is to indicate a destination memory address information corresponding to a start of a memory address log, the instruction, if executed by a machine, is to cause the machine to perform operations comprising to:
begin to log memory addresses to the memory address log, including to store memory addresses, for only all initial writes to corresponding data items, to the memory address log, wherein said initial writes represent first writes in time to the corresponding data items that occur after the instruction in original program order.

### Claim 24 (depends on 23)

The article of manufacture of claim 23, wherein the instruction, if executed by the machine, is further to cause the machine to perform operations comprising to store the data items, for said only all initial writes, before the data items are updated due to said only all initial writes, to a data item log.