# US 11,307,803 B2 · Storage device for suspending program operation and performing read operation and operating method thereof

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- Number: US 11,307,803 B2
- Document ID: US11307803B2
- Status: Granted
- Kind: B2
- Application number: 16/821,749
- Filed: 2020-03-17
- Published: 2021-03-11
- Granted: 2022-04-19
- Earliest claimed: 2019-09-06
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Beom Ju Shin; Yun Jung Yeom
- Web page: https://patentgrep.com/patent/US11307803B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0673: {Single storage device}
- G06F 9/485: {Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory controller for controlling a memory device for storing data, the memory controller, the memory controller comprising: a request transmitter for providing a program suspend request for suspending a program operation, when the memory device receives a read request from a host while the memory device is performing the program operation and a command controller for generating and outputting a program suspend command, based on the program suspend request, and outputting a cache read command or normal read command, based on a number of commands corresponding to a request received from the host, which are queued in a command queue.

## Claims

### Claim 1

A storage device comprising:
a memory device for storing data, wherein the memory device includes a page buffer in which data is temporarily stored;
a memory controller for controlling the memory device,
wherein the memory controller includes a request transmitter configured to provide a program suspend request for suspending a program operation, when the memory device receives a read request from a host while the memory device is performing the program operation, and
wherein the memory controller includes a command controller configured to generate and output a program suspend command, based on the program suspend request, and output a cache read command or normal read command, based on a number of commands of a command queue in which a command corresponding to the read request received from the host is queued; and
program data storage for communicating with the memory device, wherein the program data storage stores data output from the memory device,
wherein the memory device is configured to output program data stored in any one latch among a plurality of latches included in the page buffer to the program data storage and allocate the latch from which the program data is output as a cache latch for performing a cache read operation corresponding to the cache read command.

### Claim 2 (depends on 1)

The storage device of claim 1, wherein the command controller is configured to:
output the cache read command when the number of the commands queued in the command queue is greater than or equal to a first reference value; and
output the normal read command when the number of the commands queued in the command queue is less than the first reference value.

### Claim 3 (depends on 2)

The storage device of claim 2, wherein the command controller is configured to, when the number of the commands queued in the command queue is greater than or equal to the first reference value, output a random data output command for receiving the program data, before the command controller outputs the cache read command.

### Claim 4 (depends on 3)

The storage device of claim 3, wherein the memory device is configured to output the program data, in response to the random data output command.

### Claim 5 (depends on 4)

The storage device of claim 4, wherein the program data storage is configured to receive and store the program data.

### Claim 6 (depends on 2)

The storage device of claim 2, wherein the command controller is configured to, when a number of read commands executed by the memory device reaches a second reference value after the command controller outputs the cache read command, output a cache read suspend command for suspending a cache read operation corresponding to the cache read command.

### Claim 7 (depends on 6)

The storage device of claim 6, wherein the command controller is configured to, when the memory device suspends the cache read operation, output a random data input command for storing data stored in the program data storage in a latch allocated to perform the cache read operation among the plurality of latches included in the page buffer of the memory device.

### Claim 8 (depends on 7)

The storage device of claim 7, wherein the program data storage is configured to again output the stored data to the memory device, and
wherein the memory device is configured to store the received data in the latch allocated to perform the cache read operation.

### Claim 9 (depends on 8)

The storage device of claim 8, wherein the command controller is configured to output a resume command for again performing the program operation, and
wherein the memory device is configured to again perform a program operation corresponding to the resume command, based on data stored in the plurality of latches included in the page buffer.

### Claim 10

A method for operating a storage device including a memory device for storing data, a memory controller for controlling the memory device, and program data storage for communicating with the memory device, the method comprising:
receiving a read request from a host while the memory device is performing a program operation;
generating a program suspend command for suspending the program operation, based on the read request;
outputting program data stored in any one latch among a plurality of latches included in a page buffer of the memory device to the program data storage; and
allocating the latch from which the program data is output as a cache latch for performing a cache read operation corresponding to the cache read command; and
performing a read operation corresponding to the cache read command or normal read command, based on a number of commands of a command queue in which a command corresponding to the read request received from the host is queued, when the program operation is suspended.

### Claim 11 (depends on 10)

The method of claim 10, wherein performing a read operation corresponding to a cache read command or normal read command comprises:
performing an operation corresponding to the cache read command when the number of the commands queued in the command queue is greater than or equal to a first reference value, and
performing an operation corresponding to the normal read command when the number of the commands queued in the command queue is smaller than the first reference value.

### Claim 12 (depends on 11)

The method of claim 11, further comprising, when the number of commands queued in the command queue is greater than or equal to the first reference value, storing, in the program data storage, the program data before the operation corresponding to the cache read command is performed.

### Claim 13 (depends on 12)

The method of claim 12, further comprising outputting a random data output command for outputting the program data to the memory device.

### Claim 14 (depends on 10)

The method of claim 10, further comprising generating, when a number of read commands executed by the memory device reaches a second reference value after the cache read operation corresponding to the cache read command is started, the cache read suspend command for suspending the cache read operation corresponding to the cache read command.

### Claim 15 (depends on 14)

The method of claim 14, further comprising storing data stored in the program data storage in the latch allocated to perform the cache read operation, when the cache read operation is suspended in response to the cache read suspend command.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
generating a resume command for again performing the program operation; and
again performing the program operation, based on data stored in the plurality of latches included in the page buffer of the memory device, in response to the resume command.