# US 11,307,795 B2 · Electronic processing devices and memory control methods thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,795 B2 - Document ID: US11307795B2 - Status: Granted - Kind: B2 - Application number: 17/114,932 - Filed: 2020-12-08 - Published: 2021-06-10 - Granted: 2022-04-19 - Earliest claimed: 2019-12-09 - Assignees: Nuvoton Technology Corporation - Applicants: Nuvoton Technology Corporation - Inventors: Pin-Ren Chen; Tzu-Lan Shen - Web page: https://patentgrep.com/patent/US11307795B2 ## CPC - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 12/0638: {Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70)} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 8/65: Updates (security arrangements therefor G06F21/57) - G06F 8/654: using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories - G06F 9/4403: {Processor initialisation} - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G06F 12/1441: {for a range} - G06F 2212/1024: Latency reduction - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2212/1052: Security improvement - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An electronic processing device including a memory and a Micro Control Unit (MCU) is provided. The memory includes a first memory block and a second memory block. The MCU executes first program code stored in the first memory block to write an update program code into the second memory block, and remaps a base address for a reboot of the electronic processing device from the first memory block to the second memory block in response to successfully writing the update program code into the second memory block. After that, the MCU triggers the reboot of the electronic processing device to execute the update program code stored in the second memory block. ## Claims ### Claim 1 An electronic processing device, comprising: a memory, comprising a first memory block and a second memory block; and a Micro Control Unit (MCU), configured to execute first program code stored in the first memory block to write an update program code into the second memory block, remap a base address for a reboot of the electronic processing device from the first memory block to the second memory block in response to successfully writing the update program code into the second memory block, and trigger the reboot of the electronic processing device to execute the update program code stored in the second memory block. ### Claim 2 (depends on 1) The electronic processing device of claim 1, wherein the memory further comprises a storage space for storing a configuration, and the MCU is further configured to determine the base address for the reboot of the electronic processing device according to the configuration. ### Claim 3 (depends on 2) The electronic processing device of claim 2, wherein the first program code stored in the first memory block is executed in response to the configuration being set to a first value, and the remapping of the base address comprises setting the configuration to a second value, so as to trigger the reboot of the electronic processing device to execute the update program code stored in the second memory block. ### Claim 4 (depends on 1) The electronic processing device of claim 1, wherein the MCU is further configured to configure all or part of the first memory block as an eXecute Only Memory (XOM) and configure all or the same part of the second memory block as an XOM, to protect key program code of the first program code and the update program code. ### Claim 5 (depends on 1) The electronic processing device of claim 1, wherein the memory is an Application Program Read Only Memory (APROM) or a Serial Peripheral Interface (SPI) flash memory. ### Claim 6 A memory control method for an electronic processing device comprising a memory and an MCU, the memory control method comprising: executing first program code stored in a first memory block of the memory to write an update program code into a second memory block of the memory; remapping a base address for a reboot of the electronic processing device from the first memory block to the second memory block in response to successfully writing the update program code into the second memory block; and triggering the reboot of the electronic processing device to execute the update program code stored in the second memory block. ### Claim 7 (depends on 6) The memory control method of claim 6, wherein the memory further comprises a storage space for storing a configuration, and the memory control method further comprises: determining the base address for the reboot of the electronic processing device according to the configuration. ### Claim 8 (depends on 7) The memory control method of claim 7, wherein the first program code stored in the first memory block is executed in response to the configuration being set to a first value, and the remapping of the base address comprises setting the configuration to a second value, so as to trigger the reboot of the electronic processing device to execute the update program code stored in the second memory block. ### Claim 9 (depends on 6) The memory control method of claim 6, further comprising: configuring all or part of the first memory block as an XOM and configuring all or the same part of the second memory block as an XOM, to protect key program code of the first program code and the update program code. ### Claim 10 (depends on 6) The memory control method of claim 6, wherein the memory is an APROM or an SPI flash memory.