# US 11,307,794 B2 · Memory system, memory controller, and operation method of memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,794 B2 - Document ID: US11307794B2 - Status: Granted - Kind: B2 - Application number: 17/095,175 - Filed: 2020-11-11 - Published: 2021-12-16 - Granted: 2022-04-19 - Earliest claimed: 2020-06-16 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Seung Gu Ji; Hyung Min Lee - Web page: https://patentgrep.com/patent/US11307794B2 ## CPC - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0611: {in relation to response time} - G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Memory systems, memory controllers, and operation methods of the memory systems are disclosed. In one example aspect, the memory system may suspend a target operation, such as a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. In this way, the memory system may reduce a delay associated with the suspension of program operations and erasure operations. ## Claims ### Claim 1 A memory system comprising: a memory device including memory cells to store data and operable to perform an operation on one or more memory cells including, a read operation for reading data stored in one or more memory cells, a program operation for writing new data into one or more memory cells, or an erase operation for deleting stored data in one or more memory cells; and a memory controller in communication with the memory device and configured to control the memory device to perform an operation, wherein the memory controller is configured to: suspend a target operation that is being executed by the memory device based on i) whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and ii) a number of times the target operation is suspended, and wherein the target operation includes a program operation or an erase operation that has been in progress when suspending the target operation. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the memory controller is configured to suspend the target operation upon a determination that the first operation is not executed, and that the suspension count of the target operation is less than a first reference number of suspensions. ### Claim 3 (depends on 2) The memory system of claim 2, wherein the memory controller is configured to, when suspending the target operation after the target operation is resumed from a previous suspension, suspend the target operation only after a predetermined minimum delay time has passed since the resumption of the target operation. ### Claim 4 (depends on 3) The memory system of claim 3, the memory controller is configured to determine the predetermined minimum delay time depending on whether the suspension count of the target operation is greater than or equal to a second reference number of suspensions when the target operation is an erase operation. ### Claim 5 (depends on 1) The memory system of claim 1, wherein the memory controller is configured to resume the target operation based on whether the first operation is performed, and based on a number of the read operation executed after the target operation is suspended. ### Claim 6 (depends on 5) The memory system of claim 5, wherein the memory controller is configured to resume the suspended target operation upon a determination that the first operation is executed, or that the number of the read operation executed after the target operation is suspended is greater than or equal to a first number of read operations. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the memory controller is configured to resume the suspended target operation upon a determination that the target operation is an erase operation, and that the number of the read operation executed after the target operation is suspended is greater than or equal to a second number of read operations. ### Claim 8 (depends on 7) The memory system of claim 7, wherein the memory controller is configured to update the second number of read operations depending on whether a total number of the read operation executed while the target operation is in progress is greater than or equal to a third number of reads. ### Claim 9 (depends on 8) The memory system of claim 8, wherein the third number of read operations is proportional to the suspension count of the target operation, and a reference number of read operations per suspended operation. ### Claim 10 A memory controller comprising: a memory interface configured to communicate with a memory device; and a processor configured to communicate with the memory device through the memory interface to suspend the target operation based on whether a first operation configured to reset a reference read bias is performed upon occurrence of a failure in a read operation executed after the target operation is suspended, and based on a suspension count of the target operation, wherein the target operation includes a program operation or an erase operation that has been in progress when suspending the target operation. ### Claim 11 (depends on 10) The memory controller of claim 10, wherein the processor is configured to suspend the target operation upon a determination that the first operation is not executed, and that the suspension count of the target operation is less than a first reference number of suspensions. ### Claim 12 (depends on 11) The memory controller of claim 11, wherein the processor is configured to, when suspending the target operation after the target operation is resumed from a previous suspension, suspend the target operation only after a predetermined minimum delay time has passed since the resumption of the target operation. ### Claim 13 (depends on 12) The memory controller of claim 12, wherein the processor is configured to determine the predetermined minimum delay time depending on whether the suspension count of the target operation is greater than or equal to a second reference number of suspensions when the target operation is an erase operation. ### Claim 14 (depends on 10) The memory controller of claim 10, wherein the processor is configured to resume the target operation based on whether the first operation is performed, and based on a number of the read operation executed after the target operation is suspended. ### Claim 15 (depends on 14) The memory controller of claim 14, wherein the processor is configured to resume the suspended target operation upon a determination that the first operation is executed, or that the number of the read operation executed after the target operation is suspended is greater than or equal to a first number of read operations. ### Claim 16 (depends on 15) The memory controller of claim 15, wherein the processor is configured to resume the suspended target operation upon a determination that the target operation is an erase operation, and that the number of the read operation executed after the target operation is suspended is greater than or equal to a second number of read operations. ### Claim 17 (depends on 16) The memory controller of claim 16, wherein the processor is configured to update the second number of read operations depending on whether a total number of the read operation executed while the target operation is in progress is greater than or equal to a third number of reads. ### Claim 18 (depends on 17) The memory controller of claim 17, wherein the third number of read operations is proportional to the suspension count of the target operation, and a reference number of read operations per suspended operation. ### Claim 19 An operation method of a memory system, the method comprising: determining, while a target operation is in progress, whether a first operation configured to reset a reference read bias is performed upon occurrence of a failure in a read operation executed after the target operation is suspended, and based on a suspension count of the target operation; and suspending the target operation based on whether the first operation is performed and the suspension count of the target operation, wherein the target operation includes a program operation or an erase operation that has been in progress when suspending the target operation. ### Claim 20 (depends on 19) The operation method of claim 19, further comprising resuming the target operation based on whether the first operation is performed and based on a number of the read operation executed after the target operation is suspended.