# US 11,307,793 B2 · Memory controller, and method thereof

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- Number: US 11,307,793 B2
- Document ID: US11307793B2
- Status: Granted
- Kind: B2
- Application number: 16/951,228
- Filed: 2020-11-18
- Published: 2021-06-24
- Granted: 2022-04-19
- Earliest claimed: 2019-12-23
- Assignees: Silicon Works Co., Ltd.
- Applicants: Silicon Works Co., Ltd.
- Inventors: Jang Won Seo
- Web page: https://patentgrep.com/patent/US11307793B2

## CPC

- G06F 3/0653: {Monitoring storage devices or systems}
- G11C 29/1201: {comprising I/O circuitry}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 29/14: Implementation of control logic, e.g. test mode decoders
- G11C 29/18: Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory controller according to an aspect of the present invention includes a buffer configured to store an operation command table including operation commands entered by a user, a BIST (built-in self-tester) controller configured to generate a pointer pointing to an operation command, a command and address generator configured to decode the operation command corresponding to the pointer among the operation commands to generate first memory commands, a command and address queue comprising queues for storing the first memory commands, and a command requester configured to output a test command including first operation command information for the generation of a memory command output from a first queue included in the queues among the memory command, location information of the first queue, and the operation commands.

## Claims

### Claim 1

A main controller comprising:
a buffer configured to store an operation command table including operation commands entered by a user;
a BIST (built-in self-tester) controller configured to generate a pointer pointing to an operation command;
a command and address generator configured to decode the operation command corresponding to the pointer among the operation commands to generate first memory commands;
a command and address queue comprising queues for storing the first memory commands; and
a command requester configured to output a test command including first operation command information for the generation of a memory command output from a first queue included in the queues among the memory command, location information of the first queue, and the operation commands.

### Claim 2 (depends on 1)

The main controller of claim 1, further comprising a data generator configured to receive command information including type information of the memory command, the location information of the first queue, and the first operation command information and generate expected data corresponding to the command information.

### Claim 3 (depends on 1)

The main controller of claim 1, further comprising a comparator configured to compare the expected data generated by the data generator to read data and output a comparison signal to the BIST controller.

### Claim 4 (depends on 3)

The main controller of claim 3, wherein the BIST controller generates a stop control signal for stopping the command requester in response to the comparison signal indicating mismatching between the expected data and the read data.

### Claim 5 (depends on 3)

The main controller of claim 3, wherein when the comparison signal indicates mismatching between the expected data and the read data, the BIST controller transmits address information stored in the first queue, the expected data, and the read data to a bus interface.

### Claim 6 (depends on 3)

The main controller of claim 3, wherein when the expected data matches the read data, the comparator outputs a comparison signal indicating matching between the expected data and the read data to the BIST controller.

### Claim 7 (depends on 1)

The main controller of claim 1, further comprising:
a scheduler configured to change an execution order of memory commands to be transmitted to the memory;
a main controller configured to control the memory; and
a switch configured to connect one of an output of the scheduler and an output of the command requester to an input of the main controller.

### Claim 8 (depends on 7)

The memory controller of claim 7, wherein the main controller is configured to:
receive the memory command output from the scheduler through the switch and control an operation of the memory in response to the received memory command; and
receive the test command output from the command requester through the switch and test the memory in response to the received test command.

### Claim 9 (depends on 7)

The memory controller of claim 7, wherein
the BIST controller generates a control signal on the basis of a state signal indicating whether the scheduler is in use, and
when the state signal indicates that the scheduler is not in use, the BIST controller generates the control signal for connecting the output of the command requester to the input of the main controller and outputs the control signal to the switch.

### Claim 10 (depends on 7)

The memory controller of claim 7, wherein
the main controller generates at least one indication signal indicating information on a processable command and transmits the generated indication signal to at least one of the scheduler and the BIST controller, and
the at least one of the scheduler and the BIST controller determines whether to transmit the command corresponding to the information in response to the at least one indication signal.