# US 11,307,782 B2 · Host identification and verification system and method for a memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,782 B2 - Document ID: US11307782B2 - Status: Granted - Kind: B2 - Application number: 16/891,650 - Filed: 2020-06-03 - Published: 2021-12-09 - Granted: 2022-04-19 - Earliest claimed: 2020-06-03 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Qing Liang; Jun Huang - Web page: https://patentgrep.com/patent/US11307782B2 ## CPC - G06F 3/0632: {by initialisation or re-initialisation of storage systems} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0622: {in relation to access} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - H04L 9/3213: {using tickets or tokens, e.g. Kerberos (network architectures or network communication protocols for entities authentication using tickets in a packet data network H04L63/0807)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Methods, systems, and devices related to host identification for a memory system are described. A memory system may receive an index value from a host system that is associated with an identification of the host system. The memory system may identify one or more operating parameter associated with the index value based on receiving the index value. The memory system controller may configure the memory system to utilize one or more operating parameters associated with the index value based on identifying the operating parameters. The memory system may output an indication to the host system that the operating parameters associated with the index value are configured to be utilized by the memory system. ## Claims ### Claim 1 An apparatus, comprising; a memory system; a memory system controller associated with the memory system and configured to cause the apparatus to: receive, from a host system, an index value that is associated with an identification of the host system; identify one or more operating parameters of the memory system based at least in part on the index value associated with the identification of the host system; configure the memory system to use the one or more operating parameters based at least in part on identifying the one or more operating parameters; verify, at the memory system, the index value with a value stored by the memory system that is associated with the one or more operating parameters, wherein configuring the memory system is based at least in part on verifying the index value with the value; and output, to the host system, an indication that the memory system is configured to use the one or more operating parameters associated with the index value based at least in part on configuring the memory system. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the memory system controller is further configured to cause the apparatus to: receive, from the host system, a token value that is associated with the index value; and determine that the token value matches a second value stored by the memory system and that is associated with the one or more operating parameters, wherein verifying the index value is based at least in part on determining that the token value matches the second value. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the memory system controller is further configured to cause the apparatus to: output, to the host system, a memory system identifier; and receive, from the host system, a token value that is generated based at least in part on the memory system identifier and a security key associated with the host system, wherein verifying the index value is based at least in part on receiving the token value. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the memory system controller is further configured to cause the apparatus to: determine that the token value is different than a second value stored by the memory system and that is associated with the one or more operating parameters; and refrain from configuring the memory system to use the one or more operating parameters based at least in part on determining the token value is different than the second value. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the memory system controller is further configured to cause the apparatus to: compare the token value with a second value stored by the memory system and that is associated with the one or more operating parameters, wherein verifying the index value is based at least in part on comparing the token value with the second value. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the memory system controller is further configured to cause the apparatus to: receive, from the host system, a first command signal having a quantity of bits and comprising the index value indicated in a portion of the first command signal. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the memory system controller is further configured to cause the apparatus to: receive, from the host system, a second command signal comprising the quantity of bits, wherein the portion of the second command signal comprises one or more reserved bits. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the memory system controller is further configured to cause the apparatus to: identify from a plurality of operating parameters stored by the memory system the one or more operating parameters associated with the index value, wherein configuring the memory system is based at least in part on the identifying. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the memory system controller is further configured to cause the apparatus to: receive, from the host system, a second index value that is associated with a set of operating parameters different than the one or more operating parameters; configure the memory system to use the set of operating parameters based at least in part on receiving the second index value; and output, to the host system, a second indication that the memory system is configured to use the set of operating parameters based at least in part on configuring the memory system. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the memory system comprises a plurality of NAND memory cells. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the one or more operating parameters of the memory system comprise trim parameters of the memory system. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the memory system controller is further configured to cause the apparatus to: receive the index value as part of an initialization procedure. ### Claim 13 A non-transitory computer-readable medium storing code comprising instructions, which when executed by a processor of an electronic device, cause the electronic device to: receive, from a host system, an index value that is associated with an identification of the host system; identify one or more operating parameters for a memory system based at least in part on the index value associated with the identification of the host system; configure the memory system to use the one or more operating parameters based at least in part on identifying the one or more operating parameters; verify, at the memory system, the index value with a value stored by the memory system that is associated with the one or more operating parameters, wherein configuring the memory system is based at least in part on verifying the index value with the value; and output, to the host system, an indication that the memory system is configured to use the one or more operating parameters associated with the index value based at least in part on configuring the memory system. ### Claim 14 (depends on 13) The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor the electronic device, further cause the electronic device to: receive, from the host system, a token value that is associated with the index value; and determine that the token value matches a second value stored by the memory system and that is associated with the one or more operating parameters, wherein verifying the index value is based at least in part on determining that the token value matches the second value. ### Claim 15 (depends on 13) The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor the electronic device, further cause the electronic device to: output, to the host system, a memory system identifier; and receive, from the host system, a token value that is generated based at least in part on the memory system identifier and a security key associated with the host system, wherein verifying the index value is based at least in part on receiving the token value. ### Claim 16 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor the electronic device, further cause the electronic device to: determine that the token value is different than a second value stored by the memory system and that is associated with the one or more operating parameters; and refrain from configuring the memory system to use the one or more operating parameters based at least in part on determining the token value is different than the second value. ### Claim 17 (depends on 13) The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor the electronic device, further cause the electronic device to: receive, from the host system, a first command signal having a quantity of bits and comprising the index value indicated in a portion of the first command signal. ### Claim 18 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor the electronic device, further cause the electronic device to: receive, from the host system, a second command signal comprising the quantity of bits, wherein the portion of the second command signal comprises one or more reserved bits. ### Claim 19 A method performed by a memory system, comprising: receiving, from a host system, an index value that is associated with an identification of the host system; identifying one or more operating parameters of the memory system based at least in part on the index value associated with the identification of the host system; configuring the memory system to use the one or more operating parameters based at least in part on identifying the one or more operating parameters; verifying, at the memory system, the index value with a value stored by the memory system that is associated with the one or more operating parameters, wherein configuring the memory system is based at least in part on verifying the index value with the value; and outputting, to the host system, an indication that the memory system is configured to use the one or more operating parameters associated with the index value based at least in part on configuring the memory system. ### Claim 20 (depends on 19) The method of claim 19, further comprising: receiving, from the host system, a token value that is associated with the index value; and determining that the token value matches a second value stored by the memory system and that is associated with the one or more operating parameters, wherein verifying the index value is based at least in part on determining that the token value matches the second value. ### Claim 21 (depends on 19) The method of claim 19, further comprising: outputting, to the host system, a memory system identifier; and receiving, from the host system, a token value that is generated based at least in part on the memory system identifier and a security key associated with the host system, wherein verifying the index value is based at least in part on receiving the token value. ### Claim 22 (depends on 21) The method of claim 21, further comprising: determining that the token value is different than a second value stored by the memory system and that is associated with the one or more operating parameters; and refraining from configuring the memory system to use the one or more operating parameters based at least in part on determining the token value is different than the second value. ### Claim 23 (depends on 21) The method of claim 21, further comprising: comparing the token value with a second value stored by the memory system and that is associated with the one or more operating parameters, wherein verifying the index value is based at least in part on comparing the token value with the second value. ### Claim 24 (depends on 19) The method of claim 19, further comprising: receiving, from the host system, a first command signal having a quantity of bits and comprising the index value indicated in a portion of the first command signal. ### Claim 25 (depends on 24) The method of claim 24, further comprising: receiving, from the host system, a second command signal comprising the quantity of bits, wherein the portion of the second command signal comprises one or more reserved bits.