# US 11,307,689 B2 · Display panel, and array substrate and manufacturing thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,689 B2 - Document ID: US11307689B2 - Status: Granted - Kind: B2 - Application number: 16/772,971 - Filed: 2020-01-06 - Published: 2021-07-22 - Granted: 2022-04-19 - Earliest claimed: 2019-01-08 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Hongwei Tian; Yanan Niu; Zheng Liu - Web page: https://patentgrep.com/patent/US11307689B2 ## CPC - G06F 3/04164: {Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads} - G06F 3/0412: {Digitisers structurally integrated in a display} - H10D 86/443: {adapted for preventing breakage, peeling or short circuiting} - H10D 86/60: wherein the TFTs are in active matrices - G06F 2203/04102: Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper - G06F 2203/04103: Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present invention provides an array substrate. The array substrate includes: a backplane including a display area and a bonding area; a wiring layer provided on the backplane and exposed in the bonding area; a protective layer provided on a surface of the wiring layer away from the backplane and covering the wiring layer in the display area and the bonding area, wherein a through-hole is provided in the protective layer in the boding area; and a connection layer provided on a surface of the protective layer away from the backplane and coupled to the wiring layer through the through-hole. ## Claims ### Claim 1 An array substrate, comprising: a backplane comprising a display area, a bonding area, and a transition area provided between the display area and the bonding area; a wiring layer provided on the backplane; a protective layer provided on a surface of the wiring layer away from the backplane, and covering the wiring layer in the display area and the bonding area, wherein a through-hole is provided in the protective layer in the bonding area; and a connection layer arranged in the display area, the transition area, and the bonding area, provided on a surface of the protective layer away from the backplane, and coupled to the wiring layer through the through-hole, wherein the protective layer is not provided in the transition area. ### Claim 2 (depends on 1) The array substrate according to claim 1, further comprising: a pixel definition layer provided between the wiring layer and the protective layer, and covering the wiring layer in the display area or covering the wiring layer in the display area and the bonding area, wherein a via-hole is provided in the pixel definition layer in the bonding area to be communicated with the through-hole. ### Claim 3 (depends on 1) The array substrate according to claim 1, wherein the protective layer comprises: a first sub-protective layer covering the display area and the bonding area; and a second sub-protective layer covering the display area or covering the display area and the bonding area. ### Claim 4 (depends on 1) The array substrate according to claim 1, wherein a plurality of the through-holes are provided. ### Claim 5 (depends on 1) The array substrate according to claim 1, further comprising: a display layer provided between the wiring layer and the protective layer in the display area, wherein pixels are defined in the display layer by the pixel definition layer. ### Claim 6 (depends on 5) The array substrate according to claim 5, wherein the wiring layer comprises an electrode wiring and at least one of a source wiring and a drain wiring of a transistor for driving the display layer to emit light. ### Claim 7 (depends on 1) The array substrate according to claim 1, wherein the connection layer comprises: a touch electrode layer provided in the display area; and a touch electrode lead extended from the touch electrode layer and coupled to the wiring layer through the through-hole. ### Claim 8 A display panel, comprising: an array substrate, wherein the array substrate comprises: a backplane comprising a display area, a bonding area, and a transition area provided between the display area and the bonding area; a wiring layer provided on the backplane; a protective layer provided on a surface of the wiring layer away from the backplane, and covering the wiring layer in the display area and the bonding area, wherein a through-hole is provided in the protective layer in the bonding area; and a connection layer arranged in the display area, the transition area, and the bonding area, provided on a surface of the protective layer away from the backplane, and coupled to the wiring layer through the through-hole, wherein the protective layer is not provided in the transition area. ### Claim 9 A method for manufacturing an array substrate, comprising: providing a backplane comprising a display area, a bonding area, and a transition area provided between the display area and the bonding area; forming a wiring layer on the backplane to cover the backplane; forming a protective layer on a surface of the wiring layer away from the backplane to cover the wiring layer in the display area and the bonding area; forming a through-hole in the protective layer in the bonding area; and forming a connection layer on a surface of the protective layer away from the backplane to be coupled to the wiring layer through the through-hole, wherein the connection layer is formed in the display area, the transition area, and the bonding area, and the protective layer is not provided in the transition area. ### Claim 10 (depends on 9) The method for manufacturing an array substrate according to claim 9, further comprising, after forming the wiring layer: forming a pixel definition layer on a surface of the wiring layer away from the backplane to cover the wiring layer in the display area or cover the wiring layer in the display area and the bonding area; and forming a via-hole in the pixel definition layer in the bonding area to be communicated with the through-hole. ### Claim 11 (depends on 9) The method for manufacturing an array substrate according to claim 9, wherein forming the protective layer on the surface of the wiring layer away from the backplane comprises: forming a first sub-protective layer on the surface of the wiring layer away from the backplane to cover the display area and the bonding area; and forming a second sub-protective layer on a surface of the first sub-protective layer away from the backplane to cover the display area or cover the display area and the bonding area. ### Claim 12 (depends on 10) The method for manufacturing an array substrate according to claim 10, further comprising forming a display layer, wherein the display layer is provided between the wiring layer and the protective layer in the display area, and pixels are defined in the display layer by the pixel definition layer. ### Claim 13 (depends on 12) The method for manufacturing an array substrate according to claim 12, wherein the wiring layer comprises an electrode wiring and at least one of a source wiring and a drain wiring of a transistor for driving the display layer to emit light. ### Claim 14 (depends on 9) The method for manufacturing an array substrate according to claim 9, wherein the connection layer comprises: a touch electrode layer provided in the display area; and a touch electrode lead extended from the touch electrode layer and coupled to the wiring layer through the through-hole. ### Claim 15 (depends on 8) The display panel according to claim 8, wherein the array substrate further comprises a pixel definition layer provided between the wiring layer and the protective layer, and covering the wiring layer in the display area or covering the wiring layer in the display area and the bonding area, wherein a via-hole is provided in the pixel definition layer in the bonding area to be communicated with the through-hole. ### Claim 16 (depends on 8) The display panel according to claim 8, wherein the protective layer comprises: a first sub-protective layer covering the display area and the bonding area; and a second sub-protective layer covering the display area or covering the display area and the bonding area. ### Claim 17 (depends on 8) The display panel according to claim 8, wherein the array substrate further comprises a display layer provided between the wiring layer and the protective layer in the display area, wherein pixels are defined in the display layer by the pixel definition layer. ### Claim 18 (depends on 8) The display panel according to claim 8, wherein the connection layer comprises: a touch electrode layer provided in the display area; and a touch electrode lead extended from the touch electrode layer and coupled to the wiring layer through the through-hole.