# US 11,307,634 B1 · Maintaining historical power level metadata for dynamic voltage and frequency scaling of processor instructions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,634 B1 - Document ID: US11307634B1 - Status: Granted - Kind: B1 - Application number: 17/160,980 - Filed: 2021-01-28 - Granted: 2022-04-19 - Earliest claimed: 2021-01-28 - Assignees: Red Hat, Inc. - Applicants: Red Hat, Inc. - Inventors: Jonathan C. Masters - Web page: https://patentgrep.com/patent/US11307634B1 ## CPC - G06F 1/324: by lowering clock frequency - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G06F 1/3296: by lowering the supply or operating voltage - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Maintaining historical power level metadata for dynamic voltage and frequency scaling of processor instructions is disclosed. A power predictor receives, from a power controller that controls voltage and/or frequency of a processor core of a processor device, a processor core power quantifier that corresponds to a voltage or frequency of the processor core while executing a processor instruction. The power predictor, based on the processor core power quantifier, stores an instruction power level in association with the processor instruction. The power predictor subsequently determines that the processor instruction is to be executed by the processor core at a future point in time. The power predictor accesses the instruction power level previously stored in association with the processor instruction. The power predictor, prior to the processor instruction being executed by the processor core, communicates to the power controller a proposed power level based on the instruction power level. ## Claims ### Claim 1 A method comprising: receiving, by a power predictor from a power controller that controls voltage and/or frequency of a processor core of a processor device, a processor core power quantifier that corresponds to a voltage or frequency of the processor core while executing a processor instruction; storing, by the power predictor based on the processor core power quantifier, an instruction power level in association with the processor instruction; subsequently determining, by the power predictor, that the processor instruction is to be executed by the processor core at a future point in time; accessing the instruction power level previously stored in association with the processor instruction; and prior to the processor instruction being executed by the processor core, communicating, by the power predictor to the power controller, a proposed power level based on the instruction power level. ### Claim 2 (depends on 1) The method of claim 1 wherein storing, by the power predictor based on the processor core power quantifier, the instruction power level in association with the processor instruction comprises: determining a particular cache block of a plurality of cache blocks in a memory cache that corresponds to the processor instruction, each cache block comprising data that identifies a respective processor instruction and metadata about the respective processor instruction; and storing, in metadata of the particular cache block, the instruction power level. ### Claim 3 (depends on 1) The method of claim 1 wherein the proposed power level comprises a dynamic voltage and frequency scaling (DVFS) power state. ### Claim 4 (depends on 1) The method of claim 1 wherein the proposed power level corresponds to a particular frequency. ### Claim 5 (depends on 1) The method of claim 1 wherein the proposed power level corresponds to a particular voltage. ### Claim 6 (depends on 1) The method of claim 1 wherein the power predictor comprises a branch predictor and the processor instruction comprises a branch instruction, and wherein storing, by the power predictor based on the processor core power quantifier, the instruction power level in association with the processor instruction further comprises storing the instruction power level in association with the branch instruction. ### Claim 7 (depends on 6) The method of claim 6 wherein storing the instruction power level in association with the branch instruction further comprises storing the instruction power level in association with a bloom filter that corresponds to the branch instruction. ### Claim 8 (depends on 1) The method of claim 1 further comprising: receiving, by the power controller, the proposed power level; determining that the processor core is executing at a power level that differs from the proposed power level; and instructing the processor core to execute at the proposed power level. ### Claim 9 A processor device comprising: a processor core; a power controller to control voltage and/or frequency of the processor core; and a power predictor; wherein the power predictor is to: receive, from the power controller, a processor core power quantifier that corresponds to a voltage or frequency of the processor core while executing a processor instruction; store, based on the processor core power quantifier, an instruction power level in association with the processor instruction; subsequently determine that the processor instruction is to be executed by the processor core at a future point in time; access the instruction power level previously stored in association with the processor instruction; and prior to the processor instruction being executed by the processor core, communicate, to the power controller, a proposed power level based on the instruction power level. ### Claim 10 (depends on 9) The processor device of claim 9 wherein to store, by the power predictor based on the processor core power quantifier, the instruction power level in association with the processor instruction, the power predictor is further to: determine a particular cache block of a plurality of cache blocks in a memory cache that corresponds to the processor instruction, each cache block comprising data that identifies a respective processor instruction and metadata about the respective processor instruction; and store, in metadata of the particular cache block, the instruction power level. ### Claim 11 (depends on 9) The processor device of claim 9 wherein the proposed power level comprises a dynamic voltage and frequency scaling (DVFS) power state. ### Claim 12 (depends on 9) The processor device of claim 9 wherein the proposed power level corresponds to a particular frequency. ### Claim 13 (depends on 9) The processor device of claim 9 wherein the proposed power level corresponds to a particular voltage. ### Claim 14 (depends on 9) The processor device of claim 9 wherein the power predictor comprises a branch predictor and the processor instruction comprises a branch instruction, and wherein to store, by the power predictor based on the processor core power quantifier, the instruction power level in association with the processor instruction, the power predictor is further to store the instruction power level in association with the branch instruction. ### Claim 15 (depends on 14) The processor device of claim 14 wherein to store the instruction power level in association with the branch instruction, the power predictor is further to store the instruction power level in association with a bloom filter that corresponds to the branch instruction. ### Claim 16 (depends on 9) The processor device of claim 9 wherein the power predictor is further to: receive, by the power controller, the proposed power level; determine that the processor core is executing at a power level that differs from the proposed power level; and instruct the processor core to execute at the proposed power level. ### Claim 17 A non-transitory computer-readable storage medium that includes executable instructions to cause a power predictor of a processor device to: receive, from a power controller that controls voltage and/or frequency of a processor core, a processor core power quantifier that corresponds to a voltage or frequency of the processor core while executing a processor instruction; store, based on the processor core power quantifier, an instruction power level in association with the processor instruction; subsequently determine that the processor instruction is to be executed by the processor core at a future point in time; access the instruction power level previously stored in association with the processor instruction; and prior to the processor instruction being executed by the processor core, communicate, to the power controller, a proposed power level based on the instruction power level. ### Claim 18 (depends on 17) The non-transitory computer-readable storage medium of claim 17 wherein to store, by the power predictor based on the processor core power quantifier, the instruction power level in association with the processor instruction, the instructions further cause the power predictor to: determine a particular cache block of a plurality of cache blocks in a memory cache that corresponds to the processor instruction, each cache block comprising data that identifies a respective processor instruction and metadata about the respective processor instruction; and store, in metadata of the particular cache block, the instruction power level. ### Claim 19 (depends on 17) The non-transitory computer-readable storage medium of claim 17 wherein the power predictor comprises a branch predictor and the processor instruction comprises a branch instruction, and wherein to store, by the power predictor based on the processor core power quantifier, the instruction power level in association with the processor instruction, the instructions further cause the power predictor to store the instruction power level in association with the branch instruction. ### Claim 20 (depends on 17) The non-transitory computer-readable storage medium of claim 17 wherein the instructions further cause the power predictor to: receive, by the power controller, the proposed power level; determine that the processor core is executing at a power level that differs from the proposed power level; and instruct the processor core to execute at the proposed power level.