# US 11,307,604 B2 · Clamp circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,604 B2 - Document ID: US11307604B2 - Status: Granted - Kind: B2 - Application number: 17/143,382 - Filed: 2021-01-07 - Published: 2021-07-29 - Granted: 2022-04-19 - Earliest claimed: 2020-01-27 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Kshitij Yadav; Sherif Galal - Web page: https://patentgrep.com/patent/US11307604B2 ## CPC - G05F 3/242: {with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage} - G05F 3/262: {using field-effect transistors only} - H02H 9/04: responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T) - H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract In certain aspects, a clamp circuit includes a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror. The clamp circuit also includes a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror. The first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror. ## Claims ### Claim 1 A clamp circuit, comprising: a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror; and a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror; wherein the first branch of the first current mirror and the second branch of the second current mirror are coupled in series between a conductive line and a ground, and the second branch of the first current mirror and the first branch of the second current mirror are coupled in series between a voltage line and the ground. ### Claim 2 (depends on 1) The clamp circuit of claim 1, wherein the clamp circuit is configured to clamp a voltage of the conductive line to a clamp voltage. ### Claim 3 (depends on 2) The clamp circuit of claim 2, wherein the clamp voltage is approximately equal to a voltage on the voltage line. ### Claim 4 (depends on 1) The clamp circuit of claim 1, wherein the first current mirror comprises: a first transistor having a drain, a gate, and a source, wherein the drain of the first transistor is coupled to the gate of the first transistor, and the source of the first transistor is coupled to a ground; and a second transistor having a drain, a gate, and a source, wherein the gate of the second transistor is coupled to the gate of the first transistor, and the source of the second transistor is coupled to the ground. ### Claim 5 (depends on 4) The clamp circuit of claim 4, wherein each of the first transistor and the second transistor comprises an n-type metal oxide semiconductor (NMOS) transistor. ### Claim 6 (depends on 4) The clamp circuit of claim 4, wherein the first current mirror further comprises: a first source resistor between the source of the first transistor and the ground; and a second source resistor between the source of the second transistor and the ground. ### Claim 7 (depends on 4) The clamp circuit of claim 4, wherein the second current mirror comprises: a third transistor having a drain, a gate, and a source, wherein the drain of the third transistor is coupled to the drain of the first transistor; and a fourth transistor having a drain, a gate, and a source, wherein the drain of the fourth transistor is coupled to the drain of the second transistor and the gate of the fourth transistor, and the gate of the fourth transistor is coupled to the gate of the third transistor. ### Claim 8 (depends on 7) The clamp circuit of claim 7, wherein each of the third transistor and the fourth transistor comprises a p-type metal oxide semiconductor (PMOS) transistor. ### Claim 9 (depends on 7) The clamp circuit of claim 7, wherein each of the first transistor and the second transistor comprises an n-type metal oxide semiconductor (NMOS) transistor, and each of the third transistor and the fourth transistor comprises a p-type metal oxide semiconductor (PMOS) transistor. ### Claim 10 (depends on 7) The clamp circuit of claim 7, wherein the source of the third transistor is coupled to the conductive line, and the source of the fourth transistor is coupled to the voltage line. ### Claim 11 (depends on 1) The clamp circuit of claim 1, wherein the conductive line is coupled to a reference circuit configured to generate a reference voltage. ### Claim 12 (depends on 11) The clamp circuit of claim 11, wherein the conductive line is coupled between the reference circuit and an analog-to-digital converter. ### Claim 13 (depends on 1) The clamp circuit of claim 1, wherein the conductive line is coupled between a voltage source and a circuit. ### Claim 14 (depends on 1) The clamp circuit of claim 1, wherein the conductive line is coupled between a transmitter and a receiver. ### Claim 15 A system, comprising: a reference circuit configured to generate a reference voltage; an analog-to-digital converter (ADC); a conductive line coupled between the reference circuit and the ADC; and a clamp circuit coupled to the conductive line, the clamp circuit comprising: a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror; and a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror; wherein the first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror; and wherein the first current mirror comprises: a first transistor having a drain, a gate, and a source, wherein the drain of the first transistor is coupled to the gate of the first transistor, and the source of the first transistor is coupled to a ground; and a second transistor having a drain, a gate, and a source, wherein the gate of the second transistor is coupled to the gate of the first transistor, and the source of the second transistor is coupled to the ground. ### Claim 16 (depends on 15) The system of claim 15, wherein the reference circuit comprises: a current source; and a reference resistor, wherein the current source and the reference resistor are coupled in series between a first supply rail and a ground, and the conductive line is coupled between the current source and the reference resistor. ### Claim 17 (depends on 15) The system of claim 15, wherein each of the first transistor and the second transistor comprises an n-type metal oxide semiconductor (NMOS) transistor. ### Claim 18 (depends on 15) The system of claim 15, wherein the first current mirror further comprises: a first source resistor between the source of the first transistor and the ground; and a second source resistor between the source of the second transistor and the ground. ### Claim 19 (depends on 15) The system of claim 15, wherein the second current mirror comprises: a third transistor having a drain, a gate, and a source, wherein the drain of the third transistor is coupled to the drain of the first transistor; and a fourth transistor having a drain, a gate, and a source, wherein the drain of the fourth transistor is coupled to the drain of the second transistor and the gate of the fourth transistor, and the gate of the fourth transistor is coupled to the gate of the third transistor. ### Claim 20 (depends on 19) The system of claim 19, wherein each of the third transistor and the fourth transistor comprises a p-type metal oxide semiconductor (PMOS) transistor. ### Claim 21 (depends on 19) The system of claim 19, wherein each of the first transistor and the second transistor comprises an n-type metal oxide semiconductor (NMOS) transistor, and each of the third transistor and the fourth transistor comprises a p-type metal oxide semiconductor (PMOS) transistor. ### Claim 22 (depends on 19) The system of claim 19, wherein the source of the third transistor is coupled to the conductive line, and the source of the fourth transistor is coupled to a voltage line. ### Claim 23 (depends on 22) The system of claim 22, wherein the reference circuit comprises: a current source; and a reference resistor, wherein the current source and the reference resistor are coupled in series between a first supply rail and a ground, and the conductive line is coupled between the current source and the reference resistor; wherein the voltage line comprises a second supply rail, the first supply rail provides a first supply voltage, the second supply rail provides a second supply voltage, and the second supply voltage is lower than the first supply voltage. ### Claim 24 A clamp circuit, comprising: a first transistor having a drain, a gate, and a source, wherein the drain of the first transistor is coupled to the gate of the first transistor, and the source of the first transistor is coupled to a ground; a second transistor having a drain, a gate, and a source, wherein the gate of the second transistor is coupled to the gate of the first transistor, and the source of the second transistor is coupled to the ground; a third transistor having a drain, a gate, and a source, wherein the drain of the third transistor is coupled to the drain of the first transistor, and the source of the third transistor is coupled to a conductive line; and a fourth transistor having a drain, a gate, and a source, wherein the drain of the fourth transistor is coupled to the drain of the second transistor and the gate of the fourth transistor, the source of the fourth transistor is coupled to a voltage line, and the gate of the fourth transistor is coupled to the gate of the third transistor. ### Claim 25 (depends on 24) The clamp circuit of claim 24, wherein each of the first transistor and the second transistor comprises an n-type metal oxide semiconductor (NMOS) transistor, and each of the third transistor and the fourth transistor comprises a p-type metal oxide semiconductor (PMOS) transistor. ### Claim 26 (depends on 24) The clamp circuit of claim 24, wherein the conductive line is coupled between a reference circuit and an analog-to-digital converter. ### Claim 27 (depends on 24) The clamp circuit of claim 24, wherein the conductive line is coupled between a voltage source and a circuit. ### Claim 28 (depends on 24) The clamp circuit of claim 24, wherein the conductive line is coupled between a transmitter and a receiver. ### Claim 29 A method for clamping a voltage on a conductive line, comprising: coupling a first current mirror and a second current mirror into a feedback loop; coupling a first branch of the second current mirror to a voltage line; coupling a second branch of the second current mirror to the conductive line; coupling a first branch of the first current mirror to a ground; and coupling a second branch of the first current mirror to the ground. ### Claim 30 (depends on 29) The method of claim 29, wherein coupling the first current mirror and the second current mirror into the feedback loop comprises: coupling the first branch of the first current mirror in series with the second branch of the second current mirror; and coupling the second branch of the first current mirror in series with the first branch of the second current mirror.