# US 11,307,469 B2 · Array substrate, method for manufacturing array substrate, and display device

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- Number: US 11,307,469 B2
- Document ID: US11307469B2
- Status: Granted
- Kind: B2
- Application number: 15/776,193
- Filed: 2017-10-20
- Published: 2020-07-16
- Granted: 2022-04-19
- Earliest claimed: 2017-03-29
- Assignees: Boe Technology Group Co., Ltd.; Hefei Xinsheng Optoelectronics Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Hefei Xinsheng Optoelectronics Technology Co., Ltd.
- Inventors: Tao Jiang; Yunhai Wan; Binbin Cao; Xianghua Ren
- Web page: https://patentgrep.com/patent/US11307469B2

## CPC

- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- G02F 1/1333: Constructional arrangements; {Manufacturing methods}(G02F1/135, G02F1/136 take precedence)
- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/133302: {Rigid substrates, e.g. inorganic substrates}
- G02F 1/134372: {for fringe field switching [FFS] where the common electrode is not patterned}
- G02F 1/13625: {Patterning using multi-mask exposure}
- G02F 2201/121: common or background
- G02F 2201/123: pixel
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure provides an array substrate and a manufacturing method of the array substrate, a display device. An array substrate comprises: a pixel array, each pixel in the pixel array having a pixel electrode; a transistor array, each transistor in the transistor array having a source electrode; and a connection electrode for electrically connecting the pixel electrode to a corresponding source electrode.

## Claims

### Claim 1

An array substrate, comprising:
a plurality of pixels, each of the plurality of pixels having: a pixel electrode; and a common electrode electrically connected to a common electrode of an adjacent pixel of the plurality of pixels;
one or more transistors, each of the one or more transistors having a source electrode; and
a connection electrode for electrically connecting the pixel electrode to a corresponding source electrode,
wherein the pixel electrode and the corresponding source electrode both directly contact a same surface of the connection electrode, the pixel electrode does not directly contact the corresponding source electrode, the connection electrode is disposed in a same layer as the common electrode, the connection electrode and the common electrode are formed simultaneously by a single patterning process, and the pixel electrode and the corresponding source electrode are positioned at a same side of the connection electrode.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein the source electrode and the pixel electrode do not overlap in a direction perpendicular to the array substrate.

### Claim 3 (depends on 1)

The array substrate according to claim 1, wherein each of the one or more transistors further comprises a drain electrode, wherein a material for forming the drain electrode and the source electrode comprises Cu.

### Claim 4 (depends on 1)

The array substrate according to claim 1, wherein a material for forming the connection electrode includes indium tin oxide.

### Claim 5 (depends on 1)

A display device, comprising the array substrate according to claim 1.

### Claim 6 (depends on 1)

The array substrate according to claim 1, further comprising a substrate on which the plurality of pixels and the one or more transistors are positioned, wherein the connection electrode is between the source electrode and the substrate.

### Claim 7 (depends on 1)

The array substrate according to claim 1, further comprising a substrate on which the plurality of pixels and the one or more transistors are positioned, wherein each of the one or more transistors comprises a gate insulating layer and a gate between the substrate and the gate insulating layer.

### Claim 8 (depends on 7)

The array substrate according to claim 7, wherein each of the one or more transistors comprises an active layer, the gate insulating layer is between the gate and the active layer.

### Claim 9 (depends on 1)

The array substrate according to claim 1, wherein each of the plurality of pixels comprises a common connection electrode, the common electrode of each of the plurality of pixels is electrically connected to the common electrode of an adjacent pixel of the plurality of pixels by the common connection electrode.

### Claim 10 (depends on 9)

The array substrate according to claim 9, wherein each of the plurality of pixels comprises a common electrode line, the common electrode is electrically connected to the common connection electrode by the common electrode line.