# US 11,307,467 B2 · Electrostatic discharge circuit and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,467 B2 - Document ID: US11307467B2 - Status: Granted - Kind: B2 - Application number: 16/619,669 - Filed: 2019-05-22 - Published: 2021-10-21 - Granted: 2022-04-19 - Earliest claimed: 2019-04-17 - Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Inventors: Zhenfei Cai - Web page: https://patentgrep.com/patent/US11307467B2 ## CPC - G02F 1/136204: {Arrangements to prevent high voltage or static electricity failures} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10D 89/811: {using FETs as protective elements} - H10D 89/931: {characterised by the dispositions of the protective arrangements} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An electrostatic discharge circuit and a display panel. The electrostatic discharge circuit includes a first conductive path and a second conductive path. An input end of the first conductive path is connected to a data signal of the display panel, and an output end is connected to a first power voltage for releasing positive charge accumulated in the display panel. An input end of the second conductive path is connected to the data signal of the display panel, and an output end is connected to a second power voltage for releasing negative charges accumulated in the display panel. ## Claims ### Claim 1 An electrostatic discharge circuit for a display panel, wherein the electrostatic discharge circuit comprises: a first conductive path, wherein an input end of the first conductive path is connected to a data signal of the display panel, and an output end is connected to a first power voltage for releasing positive charge accumulated in the display panel; a second conductive path, wherein an input end of the second conductive path is connected to the data signal of the display panel, and an output end is connected to a second power voltage for releasing negative charges accumulated in the display panel; wherein the first conductive path comprises a first thin film transistor, a first storage capacitor, and a second thin film transistor; a gate and a drain of the first thin film transistor are connected to the data signal of the display panel, and a source of the first thin film transistor is connected to one plate of the first storage capacitor; and a drain of the second thin film transistor is connected to the data signal of the display panel, a gate of the second thin film transistor is connected to the other plate of the first storage capacitor, and a source of the second thin film transistor is connected to the first power voltage. ### Claim 2 (depends on 1) The electrostatic discharge circuit according to claim 1, wherein a width to length ratio of the first thin film transistor is larger than a width to length ratio of the second thin film transistor. ### Claim 3 (depends on 2) The electrostatic discharge circuit according to claim 2, wherein the first thin film transistor has a width to length ratio of more than 50:8, and the second thin film transistor has a width to length ratio of less than 10:100. ### Claim 4 (depends on 1) The electrostatic discharge circuit according to claim 1, wherein the first thin film transistor and the second thin film transistor are N-type thin film transistors. ### Claim 5 (depends on 1) The electrostatic discharge circuit according to claim 1, wherein the second conductive path comprises a third thin film transistor, a second storage capacitor, and a fourth thin film transistor; wherein a drain of the third thin film transistor is connected to the data signal of the display panel, a gate of the third thin film transistor is connected to one plate of the second storage capacitor, and a source of the third thin film transistor is connected to the second power voltage; wherein a drain of the fourth thin film transistor is connected to the other plate of the second storage capacitor, and a gate and a source of the third thin film transistor are connected to the second power voltage. ### Claim 6 (depends on 5) The electrostatic discharge circuit according to claim 5, wherein a width to length ratio of the fourth thin film transistor is greater than a width to length ratio of the third thin film transistor. ### Claim 7 (depends on 6) The electrostatic discharge circuit according to claim 6, wherein the fourth thin film transistor has a width to length ratio greater than 50:8, and the third thin film transistor has a width to length ratio less than 10:100. ### Claim 8 (depends on 5) The electrostatic discharge circuit according to claim 5, wherein the third thin film transistor and the fourth thin film transistor are N-type thin film transistors. ### Claim 9 A display panel, wherein the display panel comprises an electrostatic discharge circuit, the electrostatic discharge circuit comprising: a first conductive path, wherein an input end of the first conductive path is connected to a data signal of the display panel, and an output end is connected to a first power voltage for releasing positive charge accumulated in the display panel; a second conductive path, wherein an input end of the second conductive path is connected to the data signal of the display panel, and an output end is connected to a second power voltage for releasing negative charges accumulated in the display panel; wherein the first conductive path comprises a first thin film transistor, a first storage capacitor, and a second thin film transistor; a gate and a drain of the first thin film transistor are connected to the data signal of the display panel, and a source of the first thin film transistor is connected to one plate of the first storage capacitor; and a drain of the second thin film transistor is connected to the data signal of the display panel, a gate of the second thin film transistor is connected to the other plate of the first storage capacitor, and a source of the second thin film transistor is connected to the first power voltage. ### Claim 10 (depends on 9) The display panel according to claim 9, wherein a width to length ratio of the first thin film transistor is larger than a width to length ratio of the second thin film transistor. ### Claim 11 (depends on 10) The display panel according to claim 10, wherein the first thin film transistor has a width to length ratio of more than 50:8, and the second thin film transistor has a width to length ratio of less than 10:100. ### Claim 12 (depends on 9) The display panel according to claim 9, wherein the first thin film transistor and the second thin film transistor are N-type thin film transistors. ### Claim 13 (depends on 9) The display panel according to claim 9, wherein the second conductive path comprises a third thin film transistor, a second storage capacitor, and a fourth thin film transistor; wherein a drain of the third thin film transistor is connected to the data signal of the display panel, a gate of the third thin film transistor is connected to one plate of the second storage capacitor, and a source of the third thin film transistor is connected to the second power voltage; wherein a drain of the fourth thin film transistor is connected to the other plate of the second storage capacitor, and a gate and a source of the third thin film transistor are connected to the second power voltage. ### Claim 14 (depends on 13) The display panel according to claim 13, wherein a width to length ratio of the fourth thin film transistor is greater than a width to length ratio of the third thin film transistor. ### Claim 15 (depends on 14) The display panel according to claim 14, wherein the fourth thin film transistor has a width to length ratio greater 50:8, and the third thin film transistor has a width to length ratio of less than 10:100. ### Claim 16 (depends on 13) The display panel according to claim 13, wherein the third thin film transistor and the fourth thin film transistor are N-type thin film transistors.