# US 11,307,253 B2 · Self-test of an asynchronous circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,307,253 B2 - Document ID: US11307253B2 - Status: Granted - Kind: B2 - Application number: 17/136,198 - Filed: 2020-12-29 - Published: 2021-06-24 - Granted: 2022-04-19 - Earliest claimed: 2017-04-18 - Assignees: Cryptography Research, Inc. - Applicants: Cryptography Research, Inc. - Inventors: Matthew Pond Baker - Web page: https://patentgrep.com/patent/US11307253B2 ## CPC - G01R 31/31922: {Timing generation or clock distribution (G01R31/3191 takes precedence)} - G01R 31/31701: {Arrangements for setting the Unit Under Test [UUT] in a test mode} - G01R 31/3187: Built-in tests - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - H04L 9/36: with means for detecting characters not meant for transmission - G06F 2221/034: Test or assess a computer or a system - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal. ## Claims ### Claim 1 A method comprising: enabling, by a controller, a feedback component of an asynchronous circuit to perform a first self-test of the asynchronous circuit at a first time; verifying, by the controller, an integrity of the asynchronous circuit based on the first self-test at the first time; disabling, by the controller, the feedback component after verifying the integrity of the asynchronous circuit at the first time; enabling, by the controller, the feedback component of the asynchronous circuit to perform a second self-test of the asynchronous circuit at a second time in response to a condition of the asynchronous circuit; verifying, by the controller, the integrity of the asynchronous circuit based on the second self-test at the second time; and disabling, by the controller, the feedback component after verifying the integrity of the asynchronous circuit at the second time. ### Claim 2 (depends on 1) The method of claim 1, further comprising determining a number of values that have been generated by the asynchronous circuit, wherein the condition is the number of values that have been generated by the asynchronous circuit exceeding a threshold number. ### Claim 3 (depends on 1) The method of claim 1, further comprising determining an amount of time that has elapsed since the first time, wherein the condition is the amount of time exceeding a threshold amount of time. ### Claim 4 (depends on 1) The method of claim 1, further comprising determining a type of cryptographic operation to be performed, wherein the condition is the type of cryptographic operation to be performed. ### Claim 5 (depends on 1) The method of claim 1, wherein the asynchronous circuit comprises a first portion and a second portion, wherein enabling the feedback component comprises: providing, by the controller, a first clock signal to the first portion of the asynchronous circuit; and providing, by the controller, a second clock signal to the second portion of the asynchronous circuit. ### Claim 6 (depends on 5) The method of claim 5, wherein providing the first clock signal and the second clock signal changes the asynchronous circuit from a deterministic behavior to a non-deterministic behavior. ### Claim 7 An integrated circuit comprising: an asynchronous circuit comprising a feedback component in a feedback path of the asynchronous circuit; and a controller, operatively coupled with the asynchronous circuit, to: enable the feedback component to perform a first self-test of the asynchronous circuit at a first time; verify an integrity of the asynchronous circuit based on the first self-test at the first time; disable the feedback component after verifying the integrity of the asynchronous circuit at the first time; enable the feedback component of the asynchronous circuit to perform a second self-test of the asynchronous circuit at a second time in response to a condition of the asynchronous circuit; verify the integrity of the asynchronous circuit based on the second self-test at the second time; and disable the feedback component after verifying the integrity of the asynchronous circuit at the second time. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein the feedback component comprises a first latch and a second latch. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein, to enable the feedback component, is to: provide a first clock signal to the first latch and a second clock signal to the second latch, the first clock signal to enable the first latch and the second clock signal to not enable the second latch, the second latch being transparent when it is not enabled, and wherein the asynchronous circuit generates a value that is used in a cryptographic operation based on the first clock signal and the second clock signal. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein providing the first clock signal and the second clock signal changes the asynchronous circuit from a non-deterministic behavior to a deterministic behavior. ### Claim 11 (depends on 7) The integrated circuit of claim 7, wherein the asynchronous circuit is a random number generator to generate one or more random values that are used in a cryptographic operation. ### Claim 12 (depends on 7) The integrated circuit of claim 7, wherein the controller is further to determine a number of values that have been generated by the asynchronous circuit, wherein the condition is the number of values that have been generated by the asynchronous circuit exceeding a threshold number. ### Claim 13 (depends on 7) The integrated circuit of claim 7, wherein the controller is further to determine an amount of time that has elapsed since the first time, wherein the condition is the amount of time exceeding a threshold amount of time. ### Claim 14 (depends on 7) The integrated circuit of claim 7, wherein the controller is further to determine a type of cryptographic operation to be performed, wherein the condition is the type of cryptographic operation to be performed. ### Claim 15 A system comprising: a memory; and a processing device, operatively coupled with the memory, the processing device comprising a controller and an asynchronous circuit with a feedback component in a feedback path of the asynchronous circuit, wherein the controller is to: enable the feedback component to perform a first self-test of the asynchronous circuit at a first time; verify an integrity of the asynchronous circuit based on the first self-test at the first time; disable the feedback component after verifying the integrity of the asynchronous circuit at the first time; enable the feedback component of the asynchronous circuit to perform a second self-test of the asynchronous circuit at a second time in response to a condition of the asynchronous circuit; verify the integrity of the asynchronous circuit based on the second self-test at the second time; and disable the feedback component after verifying the integrity of the asynchronous circuit at the second time. ### Claim 16 (depends on 15) The system of claim 15, wherein the feedback component comprises a first latch and a second latch. ### Claim 17 (depends on 16) The system of claim 16, wherein, to enable the feedback component, is to: provide a first clock signal to the first latch and a second clock signal to the second latch, the first clock signal to enable the first latch and the second clock signal to not enable the second latch, the second latch being transparent when it is not enabled, and wherein the asynchronous circuit generates a value that is used in a cryptographic operation based on the first clock signal and the second clock signal, wherein providing the first clock signal and the second clock signal changes the asynchronous circuit from a non-deterministic behavior to a deterministic behavior. ### Claim 18 (depends on 15) The system of claim 15, wherein the asynchronous circuit is a random number generator to generate one or more random values that are used in a cryptographic operation. ### Claim 19 (depends on 15) The system of claim 15, wherein the controller is further to determine a number of values that have been generated by the asynchronous circuit, wherein the condition is the number of values that have been generated by the asynchronous circuit exceeding a threshold number. ### Claim 20 (depends on 15) The system of claim 15, wherein the controller is further to determine an amount of time that has elapsed since the first time, wherein the condition is the amount of time exceeding a threshold amount of time.