# US 11,307,252 B2 · Perfect detection of concurrent faults in CMOS circuits by exploiting reversible and preservative gates

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- Number: US 11,307,252 B2
- Document ID: US11307252B2
- Status: Granted
- Kind: B2
- Application number: 17/092,352
- Filed: 2020-11-09
- Published: 2021-05-13
- Granted: 2022-04-19
- Earliest claimed: 2019-11-07
- Assignees: Istanbul Teknik Universitesi
- Applicants: Istanbul Teknik Universitesi
- Inventors: Mustafa Altun; Sajjad Parvin
- Web page: https://patentgrep.com/patent/US11307252B2

## CPC

- G01R 31/319: Tester hardware, i.e. output processing circuits
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- H03K 19/00315: {in field-effect transistor circuits}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A method of perfect detection of concurrent faults in CMOS circuits, using reversible gates and preservative gates is provided. The concurrent faults occurring in the CMOS circuits are detected without being masked by the method. The method includes the following steps: Carrying out functions using the reversible gates and the preservative gates, transforming the reversible gates and the preservative gates into CMOS circuit equivalents.

## Claims

### Claim 1

A method of perfect detection of concurrent faults in CMOS circuits, using reversible gates and preservative gates, comprising the following steps:
1) carrying out functions using the reversible gates and the preservative gates, by:
1-1) providing a given logic function,
1-2) when the given logic function is an irreversible function, converting the irreversible function to a reversible function,
1-3) utilizing ET-MPMCT gates for an ESOP synthesis technique, wherein the ESOP technique synthesizes both the reversible function and the irreversible function or a use of a Fredkin synthesis technique to implement a function with a fault preservative circuit,
1-4) synthesizing the reversible function using reversible circuit synthesis techniques with reversible gate libraries,
1-5) adding an extra parity bit to perform single parity fault detection with converting all gates to preservative versions of all the gates,
2) transforming the reversible gates and the preservative gates into CMOS circuit equivalents by:
2-1) converting the reversible gates to CMOS forms of the reversible gates.

### Claim 2 (depends on 1)

The method according to claim 1, wherein step 1) comprises the following steps after step 1-1:
1-1a) providing a given logic function without taking into account if the given logic function is reversible or not,
1-1) the given logic function is checked when the given logic function is reversible or irreversible, and the given logic function is determined as a reversible function,
1-1 c) the given logic function is checked when the given logic function is reversible or irreversible, and the given logic function is determined as an irreversible function.

### Claim 3 (depends on 1)

The method according to claim 1, wherein step 2) comprises the following additional steps:
2-2) obtaining a CMOS circuit of the CMOS circuits having a perfect fault detection capability.