# US 11,307,244 B2 · Adaptive voltage scaling methods and systems therefor

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- Number: US 11,307,244 B2
- Document ID: US11307244B2
- Status: Granted
- Kind: B2
- Application number: 16/648,500
- Filed: 2018-09-28
- Published: 2020-07-16
- Granted: 2022-04-19
- Earliest claimed: 2017-10-02
- Assignees: Arm Limited
- Applicants: Arm Limited
- Inventors: Rainer Herberholz
- Web page: https://patentgrep.com/patent/US11307244B2

## CPC

- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G06F 1/3296: by lowering the supply or operating voltage
- H03K 3/0315: {Ring oscillators}
- H03K 5/134: with field-effect transistors
- H03K 19/0013: {in field effect transistor circuits}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The present techniques disclose a logic gate for an adaptive voltage scaling monitor, the logic gate comprising an inverting output and further comprising an imbalance between the drive strength of an NMOS component and a PMOS component thereof, and wherein the imbalance is operable to cause a switching delay of the gate to be primarily dependent on one of the NMOS component or the PMOS component.

## Claims

### Claim 1

A logic gate for an adaptive voltage scaling monitor, the logic gate comprising:
a first N-type metal-oxide semiconductor (NMOS) component having a number of fingers, each finger including a transistor gate;
a second NMOS component, coupled to the first NMOS component, having a transistor gate;
a first P-type metal-oxide semiconductor (PMOS) component having a number of fingers, each finger including a transistor gate;
a second PMOS component, coupled to the first PMOS component, having a transistor gate;
a first input directly coupled to the transistor gates of the first NMOS component and the transistor gates of the first PMOS component, the first input configured to provide an input signal; and
a second input directly coupled to the transistor gate of the second NMOS component and the transistor gate of the second PMOS component, the second input configured to provide an enable signal,
wherein the first NMOS component, the second NMOS component, the first PMOS component, and the second PMOS component are configured to provide an inverting output based on the input signal,
wherein the number of fingers of the first NMOS component is greater than or less than the number of fingers of the first PMOS component to provide an imbalance between a drive strength of the first NMOS component and the first PMOS component, and
wherein the imbalance is operable to cause a switching delay of the logic gate to be primarily dependent on one of the first NMOS component or the first PMOS component.

### Claim 2 (depends on 1)

The logic gate of claim 1, wherein the logic gate comprises a NAND gate.

### Claim 3 (depends on 1)

The logic gate of claim 1, wherein the logic gate comprises a NOR gate.

### Claim 4 (depends on 1)

A delay monitor for adaptive voltage scaling, the delay monitor comprising:
a first set of logic gates as claimed in claim 1; and
a second set of logic gates as claimed in claim 1.

### Claim 5 (depends on 4)

The delay monitor of claim 4, wherein the switching delay of the first set is primarily dependent on the respective NMOS components of the first set being weaker than the respective PMOS components thereof.

### Claim 6 (depends on 4)

The delay monitor of claim 4, wherein the switching delay of the second set is primarily dependent on the respective PMOS components of the second set being weaker than the respective NMOS components thereof.

### Claim 7 (depends on 4)

The delay monitor of claim 4, wherein the first set of logic gates are configured as a first ring oscillator.

### Claim 8 (depends on 7)

The delay monitor of claim 7, wherein the second set of logic gates are configured as a second ring oscillator.

### Claim 9 (depends on 4)

A method of adaptive voltage scaling for an integrated circuit, the method comprising:
monitoring, with a delay monitor as claimed in claim 4, a performance characteristic of PMOS and NMOS components on the integrated circuit;
setting a supply voltage at the integrated circuit in response to the monitored performance characteristic.

### Claim 10 (depends on 9)

The method of claim 9, wherein the performance characteristic comprises at least one of: a switching delay and frequency.

### Claim 11 (depends on 9)

The method of claim 9, wherein monitoring the performance characteristic comprises measuring the time for the pull-down transitions of first NMOS components of a first set of logic gates.

### Claim 12 (depends on 11)

The method of claim 11, wherein monitoring the performance characteristic comprises measuring the time for the pull-up transitions of first PMOS components of a second set of logic gates.

### Claim 13 (depends on 12)

The method of claim 12, comprising:
measuring, using two or more digital counters, the time for the respective pull-up and pull-down transitions within a sample period.

### Claim 14 (depends on 9)

The method according to claim 9, wherein setting a supply voltage comprises: adjusting the supply voltage to maintain the specified performance characteristic.

### Claim 15 (depends on 4)

The delay monitor according to claim 4, wherein each logic gate in the first set of logic gates comprises a NAND gate, and each logic gate in the second set of logic gates comprises a NAND gate.

### Claim 16 (depends on 9)

The method according to claim 9, wherein each logic gate in the first set of logic gates comprises a NAND gate, and each logic gate in the second set of logic gates comprises a NAND gate.

### Claim 17 (depends on 1)

The logic gate of claim 1, wherein the second input is directly coupled to gates associated with the second NMOS component of the logic gate and gates associated with the second PMOS component of the same logic gate.

### Claim 18 (depends on 9)

The method according to claim 9, wherein the second input is directly coupled to gates associated with the second NMOS component of the logic gate and gates associated with the second PMOS component of the same logic gate.