# US 11,307,243 B2 · Memory controller with integrated test circuitry

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- Number: US 11,307,243 B2
- Document ID: US11307243B2
- Status: Granted
- Kind: B2
- Application number: 16/924,321
- Filed: 2020-07-09
- Published: 2021-02-04
- Granted: 2022-04-19
- Earliest claimed: 2011-03-14
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. Ware
- Web page: https://patentgrep.com/patent/US11307243B2

## CPC

- G01R 31/2882: {Testing timing characteristics}
- G01R 31/2607: {Circuits therefor (G01R31/2642 takes precedence)}
- G01R 31/31726: {Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals}
- G11C 29/022: {in I/O circuitry}
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11C 29/16: using microprogrammed units, e.g. state machines
- G11C 29/50012: {of timing}
- H03L 7/00: Automatic control of frequency or phase; Synchronisation
- G11C 2029/0401: {in embedded memories}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

## Claims

### Claim 1

A memory system comprising:
a test-signal generator to issue a data test signal;
a memory controller integrated-circuit (IC) device having:
a test-signal wire coupled to the test-signal generator to convey the data test signal;
a write-data transmit interface to output a write data signal, the write-data transmit interface including at least one gating transistor to gate the write data signal responsive to the data test signal; and
a first data contact pad to communicate the gated write data signal away from the memory controller IC; and
a memory IC device having:
a second data contact pad bonded to the first data contact pad to receive the gated write data signal from the memory controller IC.

### Claim 2 (depends on 1)

The memory system of claim 1, the write-data transmit interface further comprising a sequential element having a clock terminal, coupled to a clock gate, and a data output terminal, the sequential element to transmit the write data signal from the data output terminal responsive to a gated clock signal.

### Claim 3 (depends on 2)

The memory system of claim 2, the write-data transmit interface further comprising a data gate coupled to the data output terminal, the data gate to gate the write data signal responsive to the data test signal.

### Claim 4 (depends on 2)

The memory system of claim 2, further comprising a second gating transistor to convey the gated clock signal to the clock terminal of the sequential element.

### Claim 5 (depends on 1)

The memory system of claim 1, the memory controller IC including the test-signal generator.

### Claim 6 (depends on 1)

The memory system of claim 1, the test-signal generator to further generate a clock test signal, the memory controller IC further having a first clock contact pad bonded to a second contact pad on the memory IC device, the first and second clock contact pads to convey the clock test signal from the memory controller IC to the memory IC.

### Claim 7 (depends on 1)

The memory system of claim 1, the memory controller IC further comprising a read-data receive interface coupled to the first data contact pad to receive a read data signal from the memory IC.

### Claim 8 (depends on 7)

The memory system of claim 7, the test-signal generator to further generate a clock test signal, the read-data receive interface including a sequential element to latch the read data signal from the memory IC responsive to the clock test signal.

### Claim 9 (depends on 1)

The memory system of claim 1, the test-signal generator further to generate a second clock test signal, the memory controller IC further comprising a test pin to transmit the second clock test signal from the memory controller IC.

### Claim 10 (depends on 1)

The memory system of claim 1, the test-signal generator further to generate a second data test signal, the memory controller IC further comprising a test pin to transmit the second data test signal from the memory controller IC.

### Claim 11

A memory system instantiated on bonded dies, the memory system comprising:
a controller die having a controller data terminal and a controller data-test terminal;
a memory die bonded to the controller die and having a memory data terminal directly connected to the controller data terminal and a memory data-test terminal directly connected to the controller data-test terminal;
the controller data terminal to communicate a data signal from the controller die of the bonded dies to the memory data terminal of the memory die;
the controller data-test terminal to communicate a data-test signal from the controller die to the memory data-test terminal of the memory die; and
at least one gating transistor on the memory die, the at least one gating transistor to gate the data signal from the controller data terminal on the controller die responsive to the data-test signal from the controller data-test terminal on the controller die.

### Claim 12 (depends on 11)

The memory system of claim 11, the controller die including a test signal generator to generate the data-test signal.

### Claim 13 (depends on 11)

The memory system of claim 11, the controller die including a second gating transistor to gate the data signal responsive to a second data-test signal.

### Claim 14 (depends on 11)

The memory system of claim 11, further comprising a clock terminal to communicate a clock signal from the controller die to the memory die.

### Claim 15 (depends on 14)

The memory system of claim 14, the controller die further comprising a sequential storage element to transmit the data signal responsive to the clock signal.

### Claim 16 (depends on 15)

The memory system of claim 15, the controller die further comprising a second gating transistor to gate the clock signal to the sequential storage element.

### Claim 17 (depends on 16)

The memory system of claim 16, the second gating transistor to gate the clock signal responsive to a clock-test signal.

### Claim 18 (depends on 17)

The memory system of claim 17, the controller die including a test signal generator to generate the clock-test signal.

### Claim 19

A method for testing a memory controller integrated on a first die and bonded to a memory device integrated on a second die, the method comprising:
generating a data-test signal on the first die;
communicating the data-test signal from the memory controller on the first die to the memory device on the second die;
communicating a data signal from the memory controller on the first die to the memory device on the second die;
gating the data signal using the data-test signal to produce a delayed data signal; and
capturing the delayed data signal using a sequential element on the first die or the second die.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
generating a clock-test signal on the first die;
communicating the clock-test signal from the memory controller on the first die to the memory device on the second die;
communicating a clock signal from the memory controller on the first die to the memory device on the second die;
gating the clock signal on the second die with the clock-test signal on the second die; and
capturing the delayed data signal in time with the gated clock signal on the second die.