# US 11,307,242 B1 · Quantum error-correction in microwave integrated quantum circuits

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- Number: US 11,307,242 B1
- Document ID: US11307242B1
- Status: Granted
- Kind: B1
- Application number: 17/066,187
- Filed: 2020-10-08
- Granted: 2022-04-19
- Earliest claimed: 2016-01-11
- Assignees: Rigetti & Co, LLC
- Applicants: Rigetti & Co, LLC
- Inventors: William J. Zeng; Eyob A. Sete; Chad Tyler Rigetti
- Web page: https://patentgrep.com/patent/US11307242B1

## CPC

- G01R 31/2851: {Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801)}
- G06N 10/00: Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N 10/20: Models of quantum computing, e.g. quantum circuits or universal quantum computers
- G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
- G06N 10/70: Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

## Claims

### Claim 1

A quantum computing system comprising:
a quantum processor cell comprising a device lattice;
a control system communicably coupled to the quantum processor cell to control the device lattice, the control system configured to:
apply a first set of two-qubit gates to qubits in a lattice cell in the device lattice, the qubits in the lattice cell comprising data qubits and ancilla qubits, the ancilla qubits in the lattice cell residing between respective nearest-neighbor pairs of the data qubits in the lattice cell;
apply a second, different set of two-qubit gates to the qubits in the lattice cell; and
after applying the first and second sets of two-qubit gates, obtaining measurement outcomes of the ancilla qubits in the lattice cell; and
determine a parity of the measurement outcomes;
wherein the quantum processor cell includes one or more of fluxonium devices and transmon devices.

### Claim 2 (depends on 1)

The quantum computing system of claim 1, wherein applying a first set of two-qubit gates comprises applying a first set of controlled-not gates, and applying a second set of two-qubit gates comprises a second, different set of controlled-not gates.

### Claim 3 (depends on 2)

The quantum computing system of claim 2, wherein at least one of the controlled-not gates is applied to qubits defined respectively by a fluxonium device and a transmon device, and applying the controlled-not gate comprises tuning an operating frequency of the fluxonium device to an operating frequency of the transmon device.

### Claim 4 (depends on 2)

The quantum computing system of claim 2, wherein at least one of the controlled-not gates is applied to qubits defined respectively a fluxonium device and a transmon device, and applying the controlled-not gate comprises tuning an operating frequency of the fluxonium device to the |1→|2 transition frequency of the transmon device.

### Claim 5 (depends on 1)

The quantum computing system of claim 1, wherein the lattice cell comprises:
transmon devices that define the data qubits; and
fluxonium devices that define the ancilla qubits.

### Claim 6 (depends on 1)

The quantum computing system of claim 1, wherein the lattice cell comprises:
fluxonium devices that define the data qubits; and
transmon devices that define the ancilla qubits.

### Claim 7 (depends on 1)

The quantum computing system of claim 1, wherein the lattice cell comprises:
a first group of fluxonium devices that define the data qubits; and
a second group of fluxonium devices that define the ancilla qubits.

### Claim 8 (depends on 1)

The quantum computing system of claim 1, wherein the lattice cell comprises:
a first group of transmon devices that define the data qubits; and
a second group of transmon devices that define the ancilla qubits.

### Claim 9

A quantum computing system comprising:
a quantum processor cell comprising a device lattice;
a control system communicably coupled to the quantum processor cell to control the device lattice, the control system configured to:
apply a first set of two-qubit gates to qubits in a lattice cell in the device lattice, the qubits in the lattice cell comprising data qubits and ancilla qubits, the ancilla qubits in the lattice cell residing between respective nearest-neighbor pairs of the data qubits in the lattice cell;
apply a second, different set of two-qubit gates to the qubits in the lattice cell; and
after applying the first and second sets of two-qubit gates, obtaining measurement outcomes of the ancilla qubits in the lattice cell; and
determine a parity of the measurement outcomes;
wherein a rectilinear lattice comprises the lattice cell.

### Claim 10 (depends on 9)

The quantum computing system of claim 9, wherein the parity is used for quantum error-correction in a surface code applied to the rectilinear lattice.

### Claim 11 (depends on 9)

The quantum computing system of claim 9, wherein the parity is used for quantum error-correction in a color code applied to the rectilinear lattice.