# US 11,305,988 B2 · Method for preparing silicon wafer with rough surface and silicon wafer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,305,988 B2 - Document ID: US11305988B2 - Status: Granted - Kind: B2 - Application number: 17/009,765 - Filed: 2020-09-01 - Published: 2022-03-03 - Granted: 2022-04-19 - Earliest claimed: 2020-09-01 - Assignees: Aac Acoustic Technologies (Shenzhen) Co., Ltd. - Applicants: Aac Acoustic Technologies (Shenzhen) Co., Ltd. - Inventors: Wooicheang Goh; Lieng Loo; Kahkeen Lai - Web page: https://patentgrep.com/patent/US11305988B2 ## CPC - B81B 3/001: {Structures having a reduced contact area, e.g. with bumps or with a textured surface} - B81C 1/00968: {Methods for breaking the stiction bond} - B81B 3/0008: {Structures for avoiding electrostatic attraction, e.g. avoiding charge accumulation} - B81B 3/0002: {Arrangements for avoiding sticking of the flexible or moving parts} - B81B 3/0005: {Anti-stiction coatings} - B81B 3/0016: {Arrangements for avoiding sticking of the flexible or moving parts not provided for in groups B81B3/0005 - B81B3/0013} - B81B 2201/0235: Accelerometers - B81C 1/0096: {For avoiding stiction when the device is in use, i.e. after manufacture has been completed} - B81C 2201/11: Treatments for avoiding stiction of elastic or moving parts of MEMS - B81C 2201/115: Roughening a surface - Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract Provided are a method for preparing a silicon wafer with a rough surface and a silicon wafer, which solves the problem in the prior art that viscous force is likely to be generated. The method includes: depositing a first film layer having a large surface roughness on a surface of a silicon wafer that has been subjected to planar planarization, and then blanket etching the first film layer to remove the first film layer. Then, the surface of the first silicon layer facing away from the substrate is further etched to form grooves and protrusions, which provide roughness, thereby forming a silicon wafer with a rough surface. When the silicon wafer approaches to another film layer, the viscous force generated therebetween is reduced, and thus the sensitivity of the MEMS device is improved and the probability of out-of-work MEMS device is reduced. ## Claims ### Claim 1 A method for preparing a silicon wafer with a rough surface, comprising: forming a substrate, wherein the substrate has a first region, a second region, and a third region along a first direction, and the first direction is perpendicular to a thickness direction of the substrate; depositing a first silicon layer on a surface of the substrate in the second region; depositing a dielectric layer on the surface of the substrate in the first region and the third region and on a surface of the first silicon layer facing away from the substrate; performing planar planarization on the dielectric layer to expose the first silicon layer and form a dielectric planar layer and a first silicon planar layer; depositing a first film layer on a side of the first silicon planar layer facing away from the substrate, wherein the first film layer is made of a material comprising amorphous silicon; and blanket etching the first film layer to remove the first film layer. ### Claim 2 (depends on 1) The method as described in claim 1, wherein the first film layer and the first silicon layer are made of the same material. ### Claim 3 (depends on 1) The method as described in claim 1, wherein the first film layer has a smaller thickness than the first silicon planar layer. ### Claim 4 (depends on 3) The method as described in claim 3, wherein the thickness of the first film layer ranges from 0.05 μm to 0.6 μm, and the thickness of the first silicon planar layer ranges from 1 μm to 4 μm. ### Claim 5 (depends on 1) The method as described in claim 1, wherein said depositing the first film layer on the side of the first silicon planar layer facing away from the substrate comprises: chemically or physically depositing the first film layer on the side of the first silicon planar layer facing away from the substrate. ### Claim 6 (depends on 1) The method as described in claim 1, wherein said performing planar planarization on the dielectric layer comprises: performing chemical mechanical planarization on the dielectric layer. ### Claim 7 (depends on 1) The method as described in claim 1, further comprising, after said blanket etching the first film layer, etching a surface of the first silicon planar layer facing away from the substrate to form grooves in the surface of the first silicon planar layer facing away from the substrate. ### Claim 8 (depends on 1) A silicon wafer, comprising: a substrate having a first region, a second region, and a third region along a first direction, the first direction being perpendicular to a thickness direction of the substrate; a dielectric planar layer disposed on the substrate in the first region and the third region; and a rough first silicon layer disposed on the substrate in the second region, wherein the silicon wafer is prepared by the method as described in claim 1 and has a rough surface.